C2020 Computer Architecture & Data Communication

This unit is now in its 3rd version.

Assessment

-------------

Assignment: 25%

Test: 25%

Exam: 50%

Important MUST-KNOW topic

- Fetch Execute cycle

- Addressings

- Replacement Policy

- Subroutine

- RPN

Chapter 1: CPU

Common interrupts that the CPU can receive

-Program: Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, and reference outside a user's allowed memory space.

-Timer: Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.

-I/O: Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions.

-Hardware failure: Generated by a failure such as power failure or memory parity error.

Chapter 6: Memory Organization

Question

A stream of address 4, 4, 2, 4, 5, 5, 2, 3, 6 is entered into a cache memory which can only contain 3 page address at a time.

Using LRU, show the status of the cache memory indicating hits if any.

Sample Answer

Chapter 7: TCP/IP & WAP

Best Regards,