Field-Programmable Gate Array

J. Hiraiwa, E. Vargas, S. Toral, “An FPGA based Embedded Vision System for Real-Time Motion Segmentation”, International Conference on Systems, Signals and Image Processing, IWSSIP 2010, pages 360-363, 2010.

K. Appiah, A. Hunter, T. Kluge, “GW4: An FPGA-driven Image Segmentation Algorithm”, WSEAS International Conference on Signal, Speech and Image Processing, SSIP 2005, Corfu Island, Greece, August 2005.

K. Appiah, A. Hunter, T. Kluge, “GW4: A Real-Time Background Subtraction and Maintenance Algorithm for FPGA Implementation”, WSEAS Transactions on Systems, pages 1741-1751, 2005.

K. Appiah, A. Hunter, “A Single-Chip FPGA Implementation of Real-time Adaptive Background Model”, IEEE Conference on Field-Programmable Technology, FPT 20005, National University of Singapore, Singapore, December 2005.

K. Appiah, A. Hunter, P. Dickinson, H. Meng, “Accelerated hardware video object segmentation: from foreground detection to connected components labelling”, Computer Vision and Image Understanding, CVIU 2010, 2010.

J. Oliveira, A. Printes, R. Freire,  E. Melcher, I. Silva, “FPGA architecture for static background subtraction in real time”, Symposium on Integrated Circuits and Systems Design , pages 26- 31, Ouro Preto, Brazil, 2006.

J. Oliveira, A. Printes, R. Freire, E. Melcher, I. Silva, “FPGA architecture for object segmentation in real time”, EUSIPCO 2006, 2006.

J. Oliveira, R. Freire, E. Melcher, E. Pelaes, “Hardware Architecture for Real Time Video-Object Segmentation from Static Background”, XVIII Congress Brasileiro de Automática, CBA 2010, September 2010.

K. Ratnayake, A. Amer, “An FPGA-based implementation of spatio-temporal object segmentation”, IEEE International Conference on Image Processing, ICIP 2006, Atlanta, GA, USA, pages 3265-3268, October 2006.

J. Athow, N. Abbasi, A. Amer, “A Real-Time FPGA Architecture of a Modified Stable Euler-Number Algorithm for Image Binarization”, Technical Report 2009-1-ATHOW, Department of Electrical and Computer Engineering Concordia University, 2009.

N. Abbasi, J. Athow, A.  Amer, “Real-time FPGA architecture of modified Stable Euler-Number algorithm for image binarization”, IEEE International Conference on Image Processing, ICIP 2009, pages 3253-3256, November 2009.

H. Jiang, H. Ardo, V. Öwall, “Hardware accelerator design for video segmentation with multi-modal background modeling”, Internatinal Symposium on Circuits and Systems, ISCAS 2005, Volume 2, pages 1142- 1145, May 2005.

H. Jiang, V. Öwall, H. Ardo, “Real-time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction”, International Conference on Video and Signal Based Surveillance AVSS 2006, 2006.

F. Kristensen, H. Hedberg, H. Jiang, P. Nilsson, V. Öwall, “An Embedded Real-Time Surveillance System: Implementation and Evaluation”, Journal of VLSI Signal Processing, 2007.

H. Jiang, H. Ardö, V. Öwall, “A Hardware Architecture for Real-Time Video Segmentation Utilizing Memory Reduction Techniques”, IEEE Transactions on Circuits and Systems for Video Technology, Volume 19, No. 2, pages 226-336, February 2009.

M. Genovese, E. Napoli, N. Petra, “OpenCV compatible real time processor for background foreground identification”, International Conference on Microelectronics, ICM 2010, Cairo, Egypt, December 2010.

M. Wojcikowski, R. Zaglewsk, B. Pankiewicz, “FPGA-Based Real-Time Implementation of Detection Algorithm for Automatic Traffic Surveillance Sensor Network”, Journal of Signal Processing Systems, December 2010.

X. Li, X. Jing, “FPGA based mixture Gaussian background modeling and motion detection”, International Conference on Natural Computation, ICNC 2011,Volume 4, pages 2078-2081, 2011.

F. Bowen, J. Lee, E. Du, “A Scalable FPGA Vehicle Monitoring and Classification Architecture”, International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2011, 2011.

R. Rodriguez-Gomez, E. Fernandez-Sanchez, J. Diaz, E. Ros, “FPGA Implementation for Real-Time Background Subtraction Based on Horprasert Model”, Volume 12, pages 585-611, Sensors 2012, January 2012.

T. Kryjak, M. Komorkiewicz, M. Gorgon, “Real-time moving object detection for video surveillance system in FPGA”, International Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, pages 209-216, 2011.

T. Kryjak, M. Komorkiewicz, M. Gorgon, “Real-time background generation and foreground object segmentation for high-definition colour video stream in FPGA device”, Journal of Real-Time Image Processing, November 2012.

R. Rodriguez-Gomez, E. Fernandez-Sanchez, J. Diaz, E. Ros, “Codebook hardware implementation on FPGA for background subtraction”, Journal of Real-Time Image Processing, 2012.

C. Sanchez,  J. Morin, C. Llanos, “Background subtraction algorithm for moving object detection in FPGA“, Southern Conference on Programmable Logic, SPL 2012, pages 1-6, March 2012 .

Y. Wang, H. Chen, “The Design of Background Subtraction on Reconfigurable Hardware”, International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pages 182-185, 2012.

M. Genovese, E. Napoli, D. De Caro, N. Petra, A. Strollo, “FPGA Implementation of Gaussian Mixture Model Algorithm for 47fps Segmentation of 1080p Video”, Journal of Electrical and Computer Engineering, Volume 2013, 2013.

M. Genovese, E. Napoli, “ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition video”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013.

M. Genovese, E. Napoli, “FPGA-based architecture for real time segmentation and denoising of HD video”, Real-Time Image, pages 389-401, 2011.

P. Gujrathi, R. Priya, P. Malathi, “Detecting Moving Object Using Background Subtraction Algorithm in FPGA”, International Conference on Advances in Computing and Communications, ICACC 2014, pages 117-120, August 2014.

H. Hu, “Hardware/Software Co-design and Implementation of a Temporal-Median-Filter-based Algorithmic Processing System for Background Subtraction”, Master Thesis, Department of Electronic Engineering, National Taiwan University of Science and Technology, 2015.

M. Imran, M. O’Nils, H. Munir, B. Thörnberg, “Low Complexity FPGA Based Background Subtraction Technique for Thermal Imagery”, ICDSC 2015, page 1-6, September 2015.

S. Arivazhagan, K. Kiruthika, “FPGA Implementation of GMM algorithm for background subtractions in video sequences”, International Conference on Computer Vision and Image Processing, CVIP 2016, 2016.

P. Janus, K. Piszczek, T. Kryjak, “FPGA Implementation of the Flux Tensor Moving Object Detection Method”, Computer Vision and Graphics, pages 486-497, September 2016.

S. Chen, T. Xu, D. Li, J. Zhang, S. Jiang, “Moving Object Detection using Scanning Camera on a High-Precision Intelligent Holder”, MDPI Sensors 2016, October 2016.

A. Safaei, Q.  Wu, Y. Yang,  "System-on-a-chip (SoC)-based hardware acceleration for foreground and background identification", Journal of the Franklin Institute, 2017.

F. Carrizosa-Corral, A. Vazquez-Cervantes, J. Montes, T. Hernandez-Díaz, J. Solano Vargas, L. Barriga-Rodriguez, J. Soto-Cajiga, H. Jimenez-Hernandez, “FPGA-SoC implementation of an ICA-based background subtraction method”, International Journal of Circuit Theory and Applications, pages 1-20, 2018.

L. Morantes-Guzman, C. Alzate, L. Castano-Londono, D. Marquez-Viloria, J. Vargas-Bonilla, "Performance Evaluation of SoC-FPGA Based Floating-Point Implementation of GMM for Real-Time Background Subtraction", WEA 2019, October 2019.

T. Nivetha, B.. Kapali, S.  Shally, "Video-Object Detection using Background Subtraction in Spartan 3 FPGA Kit", IEEE International Conference on Smart Structures and Systems, ICSSS 2020, pages 1-4,Chennai, India, 2020.

M. Abutaleb, A. Hamdy, M. Abuelwafa, E. Saad, "FPGA-based object-extraction based on multi-modal sigma-delta background estimation", International Conference on Computer, Control and Communication, 2009.

A. Rahiminezhad, M. Tavakoli  S. Sayedi, "Hardware Implementation of Moving Object Detection using Adaptive Coefficient in Performing Background Subtraction Algorithm", IEEE International Conference on Machine Vision and Image Processing, MVIP 2022, pages 1-5, 2022.

Q. Yi, "FPGA implementation of video capture and moving target detection system", IEEE International Conference on Communications Circuits and Systems, ICCCAS 2018, pages 373-377, 2018.

Y. Han, B. Lin, J. Yan, H. Li, "Hardware and Software Co-Design Approach for Background Subtraction in High-Resolution Videos”, IEEE International Conference on Image Processing, Computer Vision and Machine Learning, ICICML 2023, Chengdu, China, 2023.

S. Du, P. Cai, T. Hu, T. Ikenaga, "Automatic Foreground Detection at 784 FPS for Ultra-High-Speed Human–Machine Interactions”, IEEE Transactions on Automation Science and Engineering, Volume 19, No. 4, pages 3587-3600, 2022.

P. Cai, S. Du, T. Ikenaga, "Local Spatio-Temporal Propagation based Adaptive Model Generation and Update for High Frame Rate and Ultra-Low Delay Foreground Detection”, IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2020, pages 1-6, Gangnueng, South Korea, 2020.

T. Nivetha, B. Kapali, S. Shally, "Video-Object Detection using Background Subtraction in Spartan 3 FPGA Kit”, IEEE International Conference on Smart Structures and Systems, ICSSS 2020, pages 1-4, Chennai, India, 2020.