Fetch, Decode, Execute Cycle

Fetch, Decode, Execute Cycle

Fetch:  

• The address of the next instruction is copied from RAM into the register (PC to the MAR) 

• The instruction (at that address) is copied to the MDR  

• The PC is incremented (so that it holds the address of the next instruction) 

Decode:  

• The MDR is copied into the Current Instruction Register (CIR)  

• The instruction / data (opcode / operand) is decoded 

•  The operand (if required) is also decoded (or fetched from RAM) 

Execute  

• The instruction is carried out. 

• Each stage is designed to happen concurrently to maximise resources use (clock ticks and memory) 

EXAM TIPS

• Being able to describe the Fetch Execute cycle is typically a 4 mark question.  For 4 marks, you must describe at least one process from each stage, otherwise max 3 marks 

• Read over your notes, practice past papers, make revision mind maps or revision flash cards for each sub topic area as you cover them in school not in the summer.

• Try making short hand notes to help you learn the order, you can even write this short hand in an exam to help structure your answer e.g.

PC to MAR
MAR to MDR
Increment PC

MDR to CIR
Decode

Execute

ADDITIONAL READING

Stored Program Concept - Machine code instructions stored in main memory are fetched, decoded and executed serially by a processor that performs arithmetic and logical operations.  The stored program concept means the code is stored in main memory and executed by the CPU one instruction after the other. 

Machine Instructions

Each machine code instruction is made up of two parts: opcode and the address.

e.g. 0101 00010110 might mean store the contents of the accumulator in memory location 22.

Note:

If the opcode is 4 bits long there can be 16 different codes.

If the address is 12 bits long there can be 4096 addresses

If the address is 16 bits long there can be 65 536 addresses. (64 K)

If the address is 32 bits long there can be 4,294,967,296 addresses. (4G)