Class of 2021

• Raghav Sharma ( In Memory Compute platforms modelling )

• Shivam Sharma (In Memory Compute Bit serial Architecture)

• N Kartheek Ram Reddy (Design of Bit Serial Architecture for In-Memory Compute)

• Abhishek Bidhan (Design of Subthreshold Flip Flop)

• Shubham Pandey (Subthreshold Library Design)

• PRANJAL RAJAN (BIT SERIAL LOGIC IMPLEMENTATION FOR IMC(In memory Compute))

• Aakash Gupta (Design of Subthreshold Library)

• NEERAJ (Design of Subthreshold Library)

• Prapti Makkar (Design of Subthreshold Library)

• Prince Kumar Rauniyar (Bit serial In IMC)

Class of 2020

• Aparna Mishra (Adaptive Read Assist and Write Assist for Low Voltage SRAMs)

• Vaishali Jain (Implementation and Comparison of Error Correcting Codes and Radiation Hardening of Digital Circuits)

• Jitendra Yadav (Efficient SRAM BIST for detecting age-related fails in Automotive applications)

• Kamakshi Pandey (Layout Oriented Simulation of Radiation Hardened Flip-Flops)

• Ashish Seth (Design and Benchmark of Pulsed Latch and Nibble Pulsed Latch)

• Shashank Neeraj Dwivedi (Design of Multi-Vt Flip Flop library)

• Shaikh Tauseef Hasan (Design of Logic BIST)

• Neerupama Gupta (Optimization of Design with Multi-Vt library for different PPA targets)

• Manshi Agrawal & Juilly Sunilrao Videkar (Priority based 3-channel to 1-channel Serializer)

• Vaibhav Verma & Fiza Akhtar (Design and Benchmark of Single Ended Sense Amplifier topologies)

• Mohd Arij & Tushar Bansal (Actively Compensated Read Assist Scheme for 0.6V SRAM in 65nm)

• Shubham Saha & Kumari Anjali (BIST Algorithms to Detect Ageing related Faults in SRAMs)

• Aditya Khandelwal & Spoorthy Nagaraja (Functional Safety)

• Shubhesh Tatwadarshi (Modeling of Memory Subsystem for CNN)

Class of 2019

• Ishit Agarwal (Read Assist for Low Voltage Operation in SRAM)

• Vishal Kumar and Piyush Gupta (WL Lowering for Read Assist in SRAMs)

Class of 2021

• Prakhar Shukla (Design of Energy Efficient In-Memory Compute for GPUs)

• Mukesh Srivastav (Design of Low Power L2-Cache with 3-stage Pipeline and Burst Mode Access)

Class of 2020

• Feraj Husain (Multi-level Sense Amplifier for NVMs)

• Aakash Tyagi (Multilevel Sense Amplifier sensing for Phase Change Memory)

• Prateek Singh (Localized Voltage Drop Detection in Power Distribution Network)

Class of 2019

• Hitarth Shah (Design For Test: Identifying The Weak Retention Bits)

• Shivendra Singh (Impact And Detection Of Partial Resistive Defects and Bias Temperature Instability on SRAM Decoder)

• Vinay Patil (Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories)

• Mishal Kumar (A 32KB Wide Voltage Range Timing Speculative SRAM in 28nm CMOS)

• Mudit Awasthi (A 28Gbps Serializer Deserializer For High Speed IO Links)

• Avinash Pandit (Low Phase Noise Fast Startup Crystal Oscillator)

• Feraj Husain (A 0.4 uA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-volatile Memories in 65nm LSTP Technology )

Class of 2018

• Ankush Mamgain (Actively Controlled Retention Voltage of SRAMs)

Class of 2017

• Vikas Kumar (Weak Bit Detection in SRAMs)

Class of 2016

• Nidhi Batra (Exploration of test methodologies to detect weak bits in SRAMs)

Class of 2015

• Anil Kumar (Identification of Weak Bits in SRAMs)

Class of 2021

• Lakshay Kumar Shringey (ADCs for In-Memory-Compute)

• Gaurav Srivastav ( Analog - Current based In Memory Computation )

• Divya Sareen (Simulink Model OF IMC array (post decoder) )

• Mohammad Tabish Qumar (Analog BL current mode Compute in Memory)

• N Kartheek Ram Reddy (Design of Bit Serial Architecture for In-Memory Compute)

• Shubham Goyal (Non-Linearity Management)

• Md Adil Arif (Design of Razor flip flop for speculative computing)

• Ranjith Srinivas A B (Implementation of In memory multiplication using Bit serial architecture)

• Pulkita Gupta (Non-Linearity Management in IMC)

• Abhinav Bajoria (Non-Linearity Management in IMC)

Class of 2020

• Robinson Devasia (Hardware Accelerators for Convolutional Neural Networks)

• Sapna Sharma (Different Technologies for In-Memory Computing)

• Aditya Khandelwal (Functional Safety For Automotive Applications: Safety Mechanisms in Digital Design)

• Jitendra Yadav (Bit-Serial architectures for In-Memory Computation)

• Shuchi Nagaria (Energy Efficient Charge Pumps in NVM)

• Shivani Mamodia (Use of ML techniques in Silicon Validation)

• Shaikh Tauseef Hasan (IEEE 1149.1 JTAG Protocol)

• Surabhi Rukmangad (Machine Learning in Silicon Validation)

• Ayesha Yadav (Level Shifters for Memory Design)

• Spoorthy Nagaraja (Functional Safety For Automotive Applications: ISO26262 ASIL Requirements)

• Aman Vyas (Different Layout Topologies of a Balanced Sense Amplifier)

• Bandana Prasad (Multilevel Wordline Driver for SRAMs)

• Shaikh Tauseef Hasan (Radiation Hardened Flip Flop)

• Srashti Doser (Impact of Limiting Drive Strengths in a library on PPA of a module)

• Shivam Agarwal (Emerging Memories: MRAMs)

• Neerupama Gupta (Emerging Memories: FRAMs

• Shashank Neeraj Dwivedi (Process Variations Monitoring Circuits)

• Ashish Seth (On-Chip Characterization of Memory)

• Shaikh Tauseef Hasan (Radiation Hardened Flip Flops)

• Priyanka Kandpal (SRAM DRV Estimation Techniques)

• Feraj Husain (Transition Faults in SRAMs - Cause, Effect, and Diagnosis)

• Shubhesh Tatwadarshi (Verification of Multi-bit Accelerator)

• Aakash Tyagi (Design Failure Mode and Effect Analysis of Memory Architecture)

• Aanchal Kumari (Multi-bit Flip Flop)

• Devayanshu Mittal (Different Archtectures for On-Chip Computing and Storage)

• Vaibhav Verma (A Survey of Single-Ended Sense Amplifiers)

• Aparna Mishra (A Survey of Read and Write Assist Schemes in SRAMs)

• Srashti Doser (Figures of Merit of On-chip Temprature Sensor)

• Kamakshi Pandey (Comparison of Radiation Hardened Flip Flops)

• Aman Vyas (Inductorless DC-DC Low Power Voltage Regulators)

Class of 2019

• Avinash Pandit (Low Power Wide Tuning Range Voltage Controlled Oscillator)

• Ishan Bhatia (ASIL standards for Automotive Safety- a Memory Design Perspective)

• Ishit Agarwal (Different layouts of Voltage Latch Sense Amplifier - Impact of Structural Matching)

• Mishal Kumar (Canary and Razor Circuits in SRAMs)

• Shivendra Singh (Memory Defect Detection Based on ASIL Documentation)

• Naina Aggarwal (Impact of Supply Noise on Retention Modes in Memory)

• Swastika Kumari (To Explore and Evaluate Modifications in System Architecture for Including Razor SRAMs in High Performance and Low Power SoCs)

• Pendharkar Abhijeet Ramesh (Making Circuits Attack Proof)

• Sakshar Pathak (Low Power Low Drop Out (LDO) Regulators)

• Feraj Husain (Transition Faults in SRAM: Cause, Effect and Diagnosis)