Publications

Over the past years, our work has been published in various national and international forums. You will find a wide range of topics around Memory and Memory Subsystem Design. And, more recently, on many adjacent fields too (primarily in Digital Circuits and Systems domain).

A list with detailed citation statistics is available on my Google Scholar profile.

2021

K. Anjali, S. Saha, A. Grover, "Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders" (Accepted in VLSID 2021)
F. Husain, B. Iqbal, A. Grover, “A 0.4uA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology” (Accepted in VLSID 2021)

2020

P. Shukla, P. Singh, T. Maheshwari, A. Grover, V. Rana, "A 800MHz, 0.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP" 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020
K. Pandey, A. Grover, A. Jain, "Methodology to Estimate Robustness of Layouts of Radiation Hardened Flip-Flops to High Energy Radiations", 2020 IEEE 17th India Council International Conference (INDICON), 2020
N. Gupta, A. Grover, "300MHz to 500MHz Optimization of ARM Cortex M7 for Sensor Fusion SoCs by using Multi-threshold Libraries and Multi-bit Register cells in 16nm FinFET", 2020 IEEE 17th India Council International Conference (INDICON), 2020
B. Iqbal, M. Arij, T. Bansal, A. Grover, "Actively Compensated Read Assist Technique for 0.6 V Operation of 16 Mb High-Density SRAM in 65nm LSTP", 2020 IEEE 17th India Council International Conference (INDICON), 2020
M. Agrawal, J.S. Videkar, A. Grover, "AXI Based Three 8-Bit Parallel Input to One Serial Output Converter with Priority Management System and Asynchronous Clocks at Input and Output", 2020 IEEE 17th India Council International Conference (INDICON), 2020
R. Kumar, S. Baunthiyal, R. Tewari, D.V.S. Ganesh, A.T.C. Gowda, R. Yadav, A. Grover, "Design and Benchmark of Iso-Stable High Density 4T SRAM cells for 64MB arrays in 65nm LSTP", 2020 IEEE 17th India Council International Conference (INDICON), 2020
A. Mishra, A. Grover, “A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
M. Kumar, A. Grover, V. Dikshit, V. Gupta, “A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
S. N. Dwivedi, A. K. Seth, A. Grover, “Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
V. Verma, F. Akhtar, A. Grover, “Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
S. Singh, V. Gupta, A. Grover, K. J. Dhori, “Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder”, 2020 21st International Symposium on Quality Electronic Design (ISQED), 2020, pp. 395-400
V. Patil, A. Grover, A. Parashar, “Design of Sense Amplifier for Wide Voltage range Operation of Split Supply Memories in 22nm HKMG CMOS Technology”, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 2020, pp. 37-42

2019

V. Gupta, S. Kapur, S. Saurabh, A. Grover, “Resistive Random Access Memory: A Review of Device Challenges”, IETE Technical Review, 2019

2018

A. Mamgain, A. Grover, “A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology”, Proceedings of IEEE International System-on-Chip Conference (SOCC) 2018

2017

S. Pathak, A. Grover, M. Pohit, N. Bansal, “LoCCo-Based Scan Chain Stitching for Low Power DFT”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 25, Issue 11, pp 3227-3236, 2017
A. Grover, G.S. Visweswaran, C. Parthasarathy, M. Daud, D. Turgis, B. Giraud, J.-P. Noel, I. Miro-Panades, G. Moritz, E. Beigne, P. Flatresse, P. Kumar, S. Azmi, “A 32kb 0.35V-1.2V, 50MHz-2.5GHz Bit-Interleaved SRAM with 8T SRAM Cell and Data Dependent Write Assist in 28nm UTBB-FDSOI CMOS,” IEEE Transactions on Circuits and Systems- I: Regular Papers, Vol 69, Issue 9, pp 2438-2447, 2017
A. Ilkal, A. Grover, "Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40nm Technologies," 2017 21st International Symposium on VLSI Design and Test (VDAT), 2017

2016

S. Pathak, A. Grover, J. Singh, M. Pohit, A. S. Baghel and G. Kaur, "Scan Chain Adaptation through ECO," Asian Test Symposium (ATS) 2016
N. Batra, S. Kaushik, A. K. Gundu, M. S. Hashmi, G. S. Visweswaran and A. Grover, "A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation," Proceedings of IEEE International System-on-Chip Conference (SOCC) 2016
A G Kumar, M Hashmi & A. Grover, “A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications”, Proceedings of IEEE International Conference on VLSI Design (VLSID), 2016
P.R. Gupta, G.S. Visweswaran, G. Narang & A. Grover, “Heterogenous Memory Assembly Exploration Using a Floorplan & Interconnect Aware Framework.” Proceedings of IEEE International System-on-Chip Conference (SOCC) 2016
N. Batra, P. Sehgal, S. Kaushik, M. Hashmi, S. Bhalla & A. Grover, “Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques”, Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), 2016
N. Batra, A. K. Gundu, M. S. Hashmi, G. S. Visweswaran and A. Grover, "An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI," 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016
A. Ganguly, S. Goyal, S. Bhatia and A. Grover, "New stable loadless 6T dual-port SRAM cell design," 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

2015 & Earlier

A. Grover, G. S. Visweswaran, C. R. Parthasarathy, M. Daud, G. Moritz, J.-P. Noel, B. Giraud, D. Turgis and P. Kumar, "Low Standby Power Capacitively Coupled Sense Amplifier for Wide Voltage Range Operation of Dual Rail SRAMs," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), 2015
G. Narang, A. Fell, P. R. Gupta and A. Grover, "Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems," 2015 28th IEEE International System-on-Chip Conference (SOCC), 2015
G. Narang, P. Sharma, M. Jain and A. Grover, "Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance," Proceedings of IEEE International Conference on VLSI Design (VLSID), 2015
J. K. Yadav, P. Das, A. Jain and A. Grover, "Area compact 5T portless SRAM cell for high density cache in 65nm CMOS," 2015 19th International Symposium on VLSI Design and Test (VDAT), 2015
A. Jain, R. Malhotra, R. Kaur, A. Grover and S. Chawla, "Comparative performance evaluation of address decoding schemes: SRAM design perspective," 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2015
N. Chandoke, N. Chitkara and A. Grover, "Comparative analysis of Sense Amplifiers for SRAM in 65nm CMOS technology," 2015 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), 2015
R. Madan, R. Gupta, B. S. Nirwan and A. Grover, "Comparative analysis of SRAM cells in sub-threshold region in 65nm," International Conference on Advances in Computer Engineering and Applications, 2015
E. Beigné, A. Valentian, I. Miro-Panades ; R. Wilson ; P. Flatresse ; F. Abouzeid ; T. Benoist ; C. Bernard ; S. Bernard ; O. Billoint ; S. Clerc ; B. Giraud ; A. Grover ; J. L. Coz ; J.-P. Noel ; O. Thomas ; Y. Thonnart , "A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking," in IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 125-136, Jan. 2015
R. Wilson, E. Beigne, P. Flatresse, A. Valentian, F. Abouzeid, T. Benoist, C. Bernard, S. Bernard, O. Billoint, S. Clerc, B. Giraud, A. Grover, J. L. Coz, I. M. Panadez, J.-P. Noel, B. Pelloux-Prayer, P. Roche, O. Thomas, Y. Thonnart, D. Turgis, F. Clermidy and P. Magarshack, "A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP Embedding Fmax Tracking," Proceedings of IEEE International Solid State Circuits Conference (ISSCC), 2014
E. Beigne, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia, P. Flatresse, J.-P. Noel, F. Abouzeid, B. PellouxPrayer, A. Grover, S. Clerc, P. Roche, J. Le Coz, S. Engels and R. Wilson, "Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs", Proceedings of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
G. Moritz, B. Giraud, J.-P. Noel, D. Turgis and A. Grover, "Optimization of a Voltage Sense Amplifier Operating in Ultra Wide Voltage Range with Back Bias Design Techniques in 28nm UTBB FD-SOI Technology," Proceedings of IEEE International Conference on Design & Technology (ICICDT), 2013
B. Giraud, J.-P. Noel, A. Grover, O. Thomas, G. Moritz, M. Daud, T. Benoist, Y. Maneglia & D. Turgis, “SRAM Design in 28nm UTBB FDSOI”, Tutorial at FETCH Conference 2013