JB's Guides

Drafted by JB Bahrenburg, last modified on 4/19/2024

Starting Out

Once you have gotten your Cadence account set up and the necessary applications downloaded (refer to the Getting Started page for information on how to do this) it’s time to begin learning how to use the Cadence applications. For a series of short training tutorials, refer to the OrCAD Crash Courses section. However, I would recommend beginning with the Allegro Design Entry Using OrCAD Capture training course as the easiest starting point. Cadence offers learning maps on their site which can be used to determine a path to learning the Cadence software as well as deciding which courses to take. 

Once the proper files and documents have been downloaded you can begin with module 1. This program contains 7 learning modules as well as 2 additional informational modules about the course. The learning modules are fairly straightforward, covering basics of the Capture software, and easy to follow. Each of the labs will walk you through the actions taught in the lecture step by step.

Resources

Since this is mainly an introductory course to using the OrCAD Capture application, there are not many additional resources that may be of use outside of the course itself. However for those interested you can check out the OrCAD Capture Datasheet to learn more about the features and capabilities of the OrCAD application.

Module 3: Project Setup

This section covers the basic creation and setup of a Design Entry HDL project. The lab is fairly straightforward, however in step 5 of the "setting up a project" section, the lab mentions specifying the path to where the project will be stored. The lab says to simply add "\ram" to the end of the file path, which should be done, but first I would recommend going and creating the ram folder within the ftb folder in your file manager. Some computers may not automatically create the folder when a path which points to a file that does not exist is entered, and will prompt an error instead.

Click Install and the installation process will begin. Once this has completed you can open the PCB Editor 17.4 application, then open your *.brd file within the app. Run the auto router within the program, the steps will be the same as outlined in the lab manual. After the auto router has finished, you can now save the file, close the PCB Editor 17.4 app and reopen the routed file in the Allegro PCB Editor 2022 program. At this point you can complete the rest of the lab using only the Allegro PCB Editor 2022 application.

Module 8: Engineering Changes

The final learning module for this course, this section covers some design synchronization between Design Entry HDL and the PCB Editor. This will allow you to make changes in one program and update the other program. The module will also cover some basic project management, such as copying projects.

Resources

• Getting Started page for information on the Cadence Download Manager and any other questions regarding the installation process

Module 3: Setting Up a Library Project

Module 3 covers the setup process for a new library project as well as the part developer. To perform these tasks you will need to be using one of the library authoring or librarian products mentioned in the module 2 section, depending on which software edition you are using.

Module 4: The Symbol View

This module is incredibly important as it covers the symbol view of a new schematic symbol. The lab will cover the creation of the symbol view, which involves editing the pins, pin placement, labeling, etc. of the schematic symbol. This will also cover some basics of using the part developer, the application used to create new schematic symbols.

Module 5: The Chips View

Similar to module 4, this module is incredibly important as it ties into the part creation process. This time the lab will cover pin mapping and package definition. This step is integral if you plan on bringing your schematic over to the PCB Editor as your part will need a PCB Footprint (package definition) and will need to have pins correlating to the I/O of the package. For more information on IC packages refer to the resources entry of this guide section.

Module 6: The Part Table View

The final step in the part creation process, this module covers assigning properties to your new part. The lab also covers the final necessary information relating to the Part Developer basics.

Module 7: Testing the Part

For the second lab in this module you will need to have access to the PCB Editor software. Either the 22.1 or 17.4 software should work for this so it is up to your discretion which to choose. If the PCB Editor prompts you to select a product, make sure you select the Allegro PCB Venture option. The lab does a good job of walking you through what is needed to complete the task at hand in the PCB Editor, but for more information on operating the PCB Editor application, refer to the OrCAD Crash Courses section of this guide page.

Module 8: More Part Building

The final module covering the use of the Part Developer tool, module 8 covers some semantics of the tool's use such as copying parts and opening multiple parts. Module 8 also covers split and asymmetric parts and how they are handled or created in the Part Developer.

Module 9: Setting Up a Design Project

Module 9 dives back into using the Design Entry HDL application. This means you will need to switch back to the Allegro Venture PCB Designer Suite product if using the 22.1 software, or the Allegro Venture System Design Authoring product on the 17.4 software.

Module 11: Engineering Changes

Once again somewhat redundant, this module covers basic information such as copying projects, editing copied projects as well as repackaging. Yet again this is very good practice to nail down the concepts covered in the previous course.

Resources

• Website detailing package types. This is not too important, but different package types are discussed frequently during this course's lab, so if you find yourself curious about what the lab manual is talking about this website may help.

OrCAD Capture Constraint Manager PCB Flow

Requirements

• Access to either Capture CIS 2022 or Capture CIS 17.4 software

• Access to either PCB Editor 2022 or PCB Editor 17.4 software (both are required if using the PCB Editor 2022 software)

• Completion of the Allegro Design Entry Using OrCAD Capture course (highly recommended)

Introduction

This course covers bringing a design over from the OrCAD Capture schematic editor to the PCB Editor. This will cover many aspects of the design process and in particular the use of the constraint manager to set parameters for the PCB layout. Please note that at the moment Cadence only offers the 17.4 version of this course, but you can follow along using the 22.1 Capture software just fine. However you will need access to both the 22.1 and 17.4 PCB Editor if you choose to use the 22.1 Capture software. This guide will cover some of the differences between the 22.1 and 17.4 software as they show up in the course.

Information

Modules 1 and 5, and Database Downloads

As always you will need to begin the course by visiting the Database Downloads page and downloading all the necessary materials. Once this has been completed you can begin with module 1 which will cover the course topics and outline. Finally, module 5 simply offers a course summary and gives an overview of the material taught once you are finished with the course.

Module 2: Design Rules

The second module covers some basics of operating the constraint manager such as adding properties and creating classes. The first lab will involve modifying or adding some environment variables. The easiest way to do this in my opinion is to simply launch the environment variable page by entering Environment Variables into the windows search bar, then selecting the "Edit the system environment variables" option. This will open a new system properties window, where at the bottom you will see a button which says Environment Variables... Click the button to edit your environment variables. From here add your CDS_SITE and HOME variables but be sure to save any existing environment variables of the same name by changing the name beforehand.

Module 3: Rules Driven Layout

Module 3 involves the transition from design entry in Capture CIS to circuit board layout using the PCB Editor. If using the 22.1 Capture CIS software, you will find the *.brd file in the project manager within the layout folder. To launch the PCB Editor you can either double click on the *.brd file or you can right click the file then select Launch PCB Editor. In lab 3-4 for this section you will be asked to use the automatic router in the PCB Editor. If you have already done the Allegro Design Entry HDL Front-to-Back Flow course then you should be familiar with the issue that arises from this. Since we do not yet have access to the 22.1 routing license, you must use the 17.4 software to run the auto router. For instructions on how to install the 17.4 software, refer to the getting started guide section. Once this software has been installed, you can simply open the *.brd file you were working on in the 17.4 software, follow the lab instructions on running the auto router, then save the changes made to the file and reopen it in the 22.1 software. One of the biggest differences between the 22.1 and 17.4 software that shows up in the lab is the design synchronization tool. In the 22.1 software there is no one "Design Sync" button as there is in the 17.4 edition. Instead there are two options. If you have made changes in the schematic editor, then choose Update Layout to sync the PCB design. If you have made changes in the PCB Editor then choose the Update Schematic to sync the schematic design. Aside from this the update layout and update schematic windows should look very similar to the design sync window from the 17.4 software and should be easy to follow along with.

Resources

• Website to learn about package types as they are once again mentioned in this lab

Module 6: Creating a Hierarchical Design

Module 6 covers hierarchical designs as well as importing design files from other Cadence products and importing user-created libraries. The lab of this section will have you use the Project Manager and DE-HDL software. If you have never launched these products before then choose the Allegro Venture PCB Designer Suite product regardless of the software edition you are using.

Module 7: Design Rules

This module introduces the constraint manager once again. Using the constraint manager in System Capture is very similar to using it in OrCAD Capture or DE-HDL, so this module should seem pretty familiar at this point. Make sure to still be thorough when going through the labs as the changes made in the constraint manager are important for when the design is transferred to the PCB Editor.

Module 8: Rules Driven Layout

The final learning module covers transferring the design from the schematic editor to the PCB Editor as well as back annotating the schematic from the PCB Editor. This module's labs gave me quite a bit of issues, the first of which involved the part manager again. The first lab involves generating a netlist, however an error was prompted when trying to do this due to the part manager not being updated. However this time the part manager could not be auto updated because it needed a part to be manually updated. For this instance the part that needed updating was the RAM TC55B4257 part. To manually update a part there are two ways to go about it. First you can open the part manager and select Details. From here filter the list of parts by Manual Sync and then select the Select a part for replacement button for the part that needs to be manually synced. In my case this didn't work so I chose the second way to solve this issue. I simply used the unified search to find a library version of the chip I needed and replaced all the parts that needed to be manually synced.

Resources

• The SamacSys website. They create PCB libraries, schematic symbols, and PCB footprints, may be cool to do some digging on their site.

• Component Search Engine website, can be used to search for parts, very similar to the Unified Search window in System Capture.

Module 7: Transient Analysis

This next analysis method will measure the circuit's response in the time domain. In this lab I had some troubles copying the project. If you encounter these same issues I would recommend simply using the original file to complete the lab, or restarting System Capture and trying to re-copy the project.

Module 9: Transformers

This module covers creating and simulating several different types of transformers. As always, remember to include the PSpice libraries in each new project you create in order to access the proper parts and simulation models necessary.

Module 10: Parametric Analysis

Module 10 introduces a new kind of analysis, parametric, which involves using a parameter and viewing its effect on a circuit. This module only includes one lab which is fairly straightforward.

Below this module paragraph, I have included images of the working circuit as well as the configuration for the simulation. For the circuit, there are a couple things to note. First, the voltage source V2 is a vsrc part for which you will need to assign the TRAN, AC and DC properties. Second, the part you see labeled Advanced Analysis Properties is a variables part from the pspice_elem library. Most of the properties will remain as the default but there are a few that need to be changed or added, so be sure to reference the below schematic and assign all the properties accordingly. Finally the reference designators and net names are very important to the simulation so copy them exactly as you see them below. For the simulation, the settings that need to be changed are pictured below, the rest of the settings will use the default. For the Stimulus page you will need to add the rf_amp.stl file. This file can be found using the following path: C:WhereverYourSysCapFileIsStored\SysCapPSpice\rf_amp\logic\rf_amp\worklib\rf_amp\psp_sim_1\profiles\rf_amp.stl. This can be added using the same process as you would add the STN0214.lib file to the Library section of the simulation profile. At this point the simulation should complete successfully, though it is important to note that the graph may not look exactly as it does in the lab manual, likely due to the polarity of some capacitors. I would not worry too much about this issue as the important part is generating a working simulation with an imported PSpice part.

Module 12: Adding New Parts

Module 12 introduces some aspects of hierarchical design, involving creating a circuit, designating it as a subcircuit and using it in another project. The first lab of this module is fairly straightforward, but the second requires some patience. First, when creating the new project, if there is a warning in the violation window regarding a syntax error in the CDS.lib file, double check the file to make sure the INCLUDE statement for the PSpice libraries and the DEFINE statement for the buffer_lib library are on different lines. When placing your buffer part it will appear in the MyParts window. If it does not show up be patient and wait for the MyParts window to load. Since this window needs to load in 28,000+ parts it may take a while to load in the buffer part, so wait for the window to say 28k+ at the top before searching for the part.

Module 13: Temperature Analysis

This module teaches how to perform a temperature analysis, which will calculate the circuit's response to different temperatures. This module only involves one lab. For this lab be sure to place the voltage probe after creating the simulation profile otherwise the probe will have no effect.

Module 15: Hierarchical Blocks and Symbols

Module 15 covers using hierarchical blocks in a circuit and simulating said circuit. The labs involve building and simulating several circuits. In lab 15-2, if you are having trouble generating or finding the proper signals, I would recommend rebuilding and re-importing the clipper circuit as there may be some issues with the original. In the same lab the manual says to type in some functions and signals in the Trace Expression field. I would instead recommend clicking and choosing the functions and signals. This can be done by first selecting DB() from the Functions or Macros field, then choosing V(OUT) from the Simulation Output Variables field. Then repeat this for V(MID).

Module 16: Analog Behavioral Modeling

The 16th module goes over simulating circuits with analog signals. This module contains four short labs. These labs are fairly straightforward, but as always remember to add the proper libraries to the project. When doing the labs be sure to add the voltage probes to the circuit after creating the simulation profile, otherwise the probes will be removed. Also note that the simulation results from labs 16-1 and 16-2 should look the same.

Later when placing the digstim1 part the program may prompt an error saying "implementation property missing", as seen to the right. At this point simply enter the name for the part mentioned in the manual then press ok to open the stimulus editor. Finally, in the simulation window the lab manual says to display the "DSTIM1:OUT" signal, however it may be difficult to find this value. Instead refer to your schematic and find the net name of the net shown below, then select this net as a trace in the simulation window. In my case the signal was named _N1, but yours may be different.

Module 18: Mixed Analog and Digital Simulation

As the title describes, this module involves simulating a circuit that contains both analog and digital elements. When performing these simulations the digital and analog signals will be shown side-by-side. This lab only has one part.

Module 19: Performance Analysis

Module 19 covers creating performance analysis graphs as well as generating functions to analyze a simulation. The second and third labs for this module require the use of the buffer project created earlier in the course. If you have lost this project or have modified it in any way, refer to the images below for the setup. When setting up the circuit make sure pin 2 for both capacitors is on top and be sure to flip the LF411 part horizontally when placing it (While placing the part right click then choose horizontal). The negative symbol should be on top and the positive symbol on the bottom. To set up the simulation, choose Time Domain (Transient), set the Run To Time as 5us and the Maximum Step Size to .01ns. Next check the Parametric Sweep box, choose Global Parameter, setting the parameter name as CVAL and give the sweep a start value of 100p, an end value of 700p, and an increment of 25p.

Module 20: Noise Analysis

Module 20 offers a way to analyze the noise of certain circuit elements. This is another short and succinct module plus lab, but as always pay close attention and be sure to follow along with the lab.

Resources

• Website where the STN0214 part can be downloaded from

Another way to access the cluster via the OnDemand website is to open a terminal session. This can be done by choosing Clusters > Palmetto Shell Access. Once the terminal has been opened you will need to enter a command to start an interactive session and launch the Cadence applications. In the terminal, enter "qsub -I -l select=1:ncpus=(number of cpus you want):mem=(GB of memory you need)gb,walltime=hr:min:sec". Look to the images below for an example. Once the session has begun you can enter a couple commands to load or view programs. Enter "module avail" to get a list of all available programs on the cluster. Enter "module avail cadence" to view all the accessible cadence programs that can be run. Finally to load a program, for example the Xcelium 22 software, enter "module load cadence/Xcelium/22". Refer to the module avail command to view the names of other cadence apps and how they can be launched. To end the interactive session enter exit.

The final way I will recommend connecting is via ssh. This is easiest if you already have a virtual machine set up on your computer, or if you already run linux or mac. This can be done by opening a terminal session and entering "ssh username@login.palmetto.clemson.edu". After this you will be prompted to enter your Clemson password as well as a duo option. Once you've begun the ssh session you will need to follow the same steps as described above to start an interactive session using the qsub command. If you would like to have GUI access while connecting to the cluster via ssh, be sure to enable X11 forwarding by including the -X tag. When connecting, your ssh command should look like the following: "ssh -X username@login.palmetto.clemson.edu". Similarly, include -X in between the -I and -l flags when entering the qsub command.

Transferring Files

If you need to transfer files to the Palmetto cluster, there are once again several options to do so. For downloading files you can use the OnDemand virtual machine, however if you have files on your computer that need to be on the Cluster there are several ways to transfer them. On the OnDemand website, click on Files > Home Directory. From here this will take you to a file management screen where you can transfer files from the Cluster to your computer or vice versa.

If you operate on Linux or mac (or connect to the Cluster via ssh) then you can open a terminal session and use secure file transfer to send files to your Cluster profile. To do this, find the folder to send, then enter the command scp filename username@xfer01-ext.palmetto.clemson.edu:/home/username/destination. After this is entered you will be prompted to enter your password and choose a duo option. Once this is done the program will confirm the file has been transferred and return you to your home terminal.

Module 2: Introduction to Xcelium Simulation

The second module for this course gives an overview of the Xcelium Simulator, providing information such as which languages are supported, some of the different architectures and more. There are no labs for this section of the course, but be sure to take notes on the lecture.

Module 3: The xrun Utility

Module 3 introduces the most important command provided by the Xcelium software: xrun. This command can be used to compile, elaborate, and simulate HDL files. Xrun can also be run with various command-line arguments to modify its use and purpose. The lab will cover the various ways this command can be used.

Module 4: Xrun Use Models

This module covers the various ways in which the xrun command can be used to run the compilation, elaboration, and simulation processes individually. The lab once again will cover each way to do this, and is fairly straightforward.

Module 5: Incisive to Xcelium Single-Core Migration

Module 5 provides information on the Xcelium software's single core mode. There are once again no labs for this section of the course.

Module 6: The Xcelium Multi-Core Simulator

Similar to the previous module, this module provides information on the other operating mode for Xcelium: Multi-core simulation. The point of the lab for this module is to show the difference between running a simulation in single-core mode versus multi-core mode. Because of this, when running the simulation in single-core mode, it is important to be patient as the simulation may take a while (5 minutes or so). This section of the lab can be completed, however you may choose to stop at the "Simulating Design in Multi-Core Mode" section as we do not have access to the Xcelium Multi-Core Mode license and therefore cannot complete this section of the lab.

Later on in the lab, when looking for the "trace signals" side bar, look to the left side of the Register window and expand the tab by clicking the combinational logic looking symbol. Once the sidebar has been expanded click on either of the other logic-looking symbols to trace the selected signal. Look to the image above for a look at what the window looks like.

Module 8: Executing and Analyzing a Multi-Core Example with SimVision GUI and Indago Debug Analyzer

This module will provide an example of the debug process with the Xcelium software. This module does not come with a corresponding lab.

Module 9: Race Detector

Module 9 introduces the race detector feature of the Xcelium simulator. This feature will detect any race conditions that occur in an HDL-designed system. There is one lab for this module which is fairly straightforward.

Module 10: X-Propagation

The tenth module introduces the x-propagation features of the simulator and the accompanying labs show the effects of the x-prop features. The first three labs for this module can be completed easily, however there is an issue with one of the files for the fourth lab so don't worry about any issues the simulator may give you for this section.

Module 11: X-Pessimism Solution
This module provides an example of X-pessimism and shows how the Xcelium simulator can be used to solve this issue. There are once again no labs for this section of the course.

Module 12: SystemVerilog Support and Enhancement

Module 12 covers the Xcelium features which allow for the use and operation of SystemVerilog files. There are no labs corresponding to this module.

Module 13: The Xcelium Textual Interface

This module provides information on the Xcelium "terminal" where commands can be entered to modify the simulation process. There are a couple differences between what the lab manual says and how the commands should be entered. First, when removing a stop point, be sure to enter "stop -disable stop_3". Finally, to run a simulation for a set amount of time enter "run -timepoint 50ns". This will run the simulation for 50ns.

Module 14: Debugging with SimVision and Textual/Batch Commands

This module is another "example" module which walks through an example of using the textual interface to debug a program. There are no labs for this module.

Module 15: Latest Features and Updates

As described by the title, this module simply covers the most recent features that have been added to Xcelium. Once again there are no labs for this section of the course.

Module 16: Indago Debug Flow

The final module in this course, module 16 covers the Indago debug tool, shown below. This tool is incredibly useful for debugging HDL files and can be used for viewing simulation waveforms as well. Before using Indago on the Palmetto Cluster you must load the application by entering module load cadence/VDEBUG/2209 on the command line. If the issue persists even with VDEBUG loaded, then try setting the INDAGO_ROOT variable by entering export INDAGO_ROOT=/software/commercial/cadence/VDEBUG2209. If you start encountering a long list of errors when trying to compile the run.f file, it is likely an issue with the UVMHOME environment variable. Set this variable by entering export UVMHOME=/software/commercial/cadence/XCELIUM2209/tools/methodology/UVM/CDNS-1.1d/sv/ on the command line. This should allow the xrun command to run successfully. Later on in the lab, after running the ../scripts/run.csh & command there is a vague reference to an "xrun -f lab1.f ..." command. Don't worry about this, simply move on and enter indago & and continue with the lab.

Resources

• Cadence Indago Debug Analysis page for more info on the Indago debug tool

• HDL Bits website is a great place to either practice or learn how to use Verilog. This course teaches how to use Verilog, but I personally found the HDL Bits site a little bit more informative and easier to learn from.

Finally, labs 1-3 must be completed one after the other in one session. In other words if your Palmetto Cluster session ends, you must start again from lab 1. Lab 4 is independent of the first three, however the labs for the 6th and 7th modules also connect to labs 1-3 so it may be better to do the module 6 and 7 labs, then return to lab 5-4.

Module 6: Finding Information in the Design Hierarchy

The sixth module covers getting help while using the Genus software as well as searching for objects. As mentioned in the description of the previous module, the lab for module 6 picks up where lab 3 from module 5 ends. Therefore it is best to do the labs for modules 5 (1-3), 6, and 7 all together.

Module 7: Exploring Genus GUI

Module 7 explores the GUI that comes with the Genus software. This can be launched using the gui_show command in the Genus shell. As with lab 6, this lab must be done together with the labs from modules 5 and 6. Once the GUI is opened, look for the list showing Hier Cell - dtmf_recvr_core, x LeafCells, n Blocks on the left side. If this list in the design browser does not show this item, then right click the top item and select Top Page, as seen below. 

Later, if you encounter permission issues while trying to run the "Run" executable file, run the command chmod +x Run then simply run the file by entering ./Run Verilog and the file should execute successfully.

Modules 8-11

As with the first three modules, modules 8 through 11 do not contain any labs. The lectures for these modules cover editing a netlist, datapath synthesis, debugging and reducing runtime. These are some very important parts of the synthesis process with the Genus software so continue taking notes on these lectures.

Module 12: Genus Physical Synthesis

Before beginning the lab for module 12 you will need to load a new Cadence product. Since this lab involves the use of Innovus, enter module load cadence/DDIEXPORT/22 to load this software. Once this has been done you can begin the lab. This lab involves many steps and many different functions being used so be very careful to enter commands in properly. Once you have begun the lab, do not worry about the step to set the innovus executable path. If you have properly loaded the DDIEXPORT software then the path for the innovus executable will already be set. When you reach the step to read in the lef files, make sure you enter all of them in at once, as shown in the lab manual, otherwise you may encounter errors when trying to use the "read_def" command later on. An example of this can be seen below, do not worry about the warnings, but you should check through the messages for any errors.

Module 13: Low-Power Optimization

Module 13 covers the Genus tool for power optimization. As with the last lab there are a lot of commands to be entered so be cautious when following the lab as an incorrect command can cause errors later in the lab.

Module 14: Test Synthesis

This module covers some aspects of test synthesis such as scanning and running a dft check. Once again this lab involves many commands being entered so be cautious with this process.

Modules 15-16

These modules cover using the LEC and other tools as well as the flowkit tool, respectively. There are no labs for these modules, but it is still important to follow along with the lectures to understand these tools.

Resources

• List of vim commands if you choose to use vim or gvim as you text editor and are unfamiliar with the environment

Information

Module 1 & Database Downloads

As with the previous two courses, this course is Linux-based, therefore you must download the lab database on a Linux machine and unzip it. Instructions for how to do this can be seen in the Xcelium Simulator course on this guide page. Module 1 simply provides and introduction to the course.

Module 2: The Design Environment

Module 2 introduces the GUI of the Virtuoso software, how to set preferences, how to use each window and what each window does. If the software prompts you for a license, click the session button until the software finds the proper license. One of the labs will require you to find the gpdk090.tf file. If you are having trouble finding the file, it is located in the custom_oa22/pdk/libs.oa22/gpdk090 file. Finally, if you need to find the float icon for the palette side bar, look to the top right of the window, as seen below.

Module 3: The User Interface

The third module covers the palette and the windows displayed within it (for example the layout or objects windows), as well as some other aspects of the GUI. When you open the GUI the layout window should already be displayed in the palette. However, if it is not, change the workspace configuration to Classic and it should appear.

Module 5: Design Rule Driven, Hierarchical Design and XStream In and Out

The final module covers some basics of viewing hierarchy and the importing and exporting translator. Once again you will need to be operating in the custom_oa22 directory for these labs. One final note, the save variant button of the create via isn't labeled (though it is the standard floppy disk symbol), but for reference the image below shows where to find it in the middle of the window.

Lab 2: Multiplexer

For lab 2 you must design a simple multiplexer using a case statement. Be sure to include the timeunit and timeprecision directives. Since they are included in the testbench, they must also be included in the behavioral module. Check the testbench for guidance on how to implement these directives. The lab also requires you to use an always_comb procedural block, an example of how to use this can be seen below:

always_comb end

/* Code goes here */

end

Notice that there is no need for a sensitivity list or any synchronization since we are implementing purely combinational logic with this block.

Lab 3: ALU

As with the previous lab, remember to include the timeunit and timeprecision statements in order for the module to operate successfully. These statements can be found in the *_test.sv file for reference. For the module, the output ports should be declared as register ports. Since they are being assigned values within a procedural block, they need to be register variables in order to be driven correctly.

Lab 4: Simple Register

This lab introduces combinational logic and a new procedural block. Since we are implementing a register here, we need to use a synchronous, combinational circuit. This can be done using the always_ff procedural block. Since there is also an asynchronous, active-low reset, the negative edge of this input needs to be included in the sensitivity list of the procedural block. The block should look similar to the one seen below:

always_ff @ (posedge clk or negedge rst_) begin

/* Code goes here */

end

Lab 5: ALU Using SystemVerilog Packages

Lab 5 introduces the SystemVerilog feature of packages. These serve as a sort of directive for the compiler, pulling together multiple type definitions, functions, etc that can be imported and used in designs. They can be somewhat difficult to understand, so use the website listed below to learn more about them. This lab asks us to define the opcode enumeration type, then modify the existing case statement to use the enumeration definitions. The package containing the enumeration should be written at the top of the alu file, and no changes need to be made to the testbench file.

Lab 6: Simple Counter

This lab is very straightforward. It uses some constructs already covered in previous labs, such as the always_ff procedural block, to implement a special counter register. Remember to always include the timeunit and timeprecision directives which, as always, can be found within the testbench file for reference.

Lab 7: State Machine

For the final lab we are asked to create a controller for a simple processing system. To begin, the testbench for this file includes some hierarchical lookups needed for the test. If elements of the behavioral file are not named properly, they can cause errors. Be sure to check the testbench for reference of how elements of the behavioral module should be named.

Resources

• Information on SystemVerilog packages, these can be rather confusing to implement so use this resource for more information on using them

Module 6: Power Planning

There are no labs for this module.

Module 7: Routing Power with Special Route

The labs corresponding to module 7 pick up where lab 5 leaves off. If you can, leave the floorplan or Innovus session from lab 5 open once finished, otherwise the setup should be re-imported using the same steps from part 1 of lab 5-1. During the lab you are asked to source a setup file. To do this, go to the Innovus terminal and enter the command source dtmf.setup in order to run the setup script. Later on when trying to view the power analysis log file, you will need to enter some commands in the Innovus terminal once again. Start by entering cd run1 to change to the "run1" directory. Then enter gvim DTMF_CHIP.rpt to open the analysis log file. Keep in mind you do not need to use gvim as your file viewer, this is just my preference. Other options include vim and more. Once you have closed the file enter cd ../ to return to the working directory.

Modules 8-9

There are no labs for modules 8 and 9.

Module 10: Analyzing Route Feasibility with the Early Global Router

Module 10 covers the basics of the key steps in IC design of Placement (determining where blocks will go on the IC) and Routing (connecting each of the blocks using nets). The first lab will cover the placement aspect of it and the second lab will cover the routing aspect. Be sure to save the design once complete as this design will be needed later on in module 12.

Module 11

There are no labs for module 11.

Module 12: Extracting Parasitics and Running Timing Analysis

This module covers another step in the VLSI design flow, timing analysis. This step comes after the blocks have been placed and the design has been routed. When first beginning the lab, you may need to open the pr.inn design which was saved during module 10. When opening this design via the Restore Design if you encounter issues, the saved editions of the Innovus files can be found in the main FPR directory under pr.inv.dat. I find it best to source this file via the command read_db ../saved/pr.inv.dat instead of the Restore Design feature as this seems to work better.

Module 13

There are no labs for Module 13.

Module 14: Implementing the Clock Tree

This lab covers creating and viewing the clock tree during clock tree synthesis. To begin the lab I would recommend following the steps given in the lab manual to load the pr.inv.dat file using the read_db command instead of loading the file saved during previous labs. This will help avoid any issues or complications arriving from the saved file. Later on, a routedExtracted.inv.dat file will need to be used. This file can simply be found within the "work" directory.

Module 15: Detail Routing for Signal Integrity, Timing, Power and Design for Yield

As with the previous lab, the best step in starting this lab is to use the read_db command. This command can be run as follows: read_db ../saved/postCTSopt.inv.dat. This should load the proper file and starting point for this lab. After this step the lab should be fairly straightforward.

Module 16: Wire Editing

Module 16 introduces drawing and editing wires within the Innovus software. To begin you must open the EditRoute.dat file stored within the EDIT_ROUTE directory. This should be rather straightforward as this should be the directory from which you launched the Innovus software. Prior to creating a wire and connecting two pins, you must first select the 'refclk' pin and copy that name into the field of the edit route form. To select this pin, draw a box around the entire pin using the left button on the mouse. Now the 'Copy From Selected' button in the edit route form can be used.

Later on, when editing which metal a net is, begin by selecting the net you wish to change. Next, click the pull down menu on the 'Change Layer' button. Then select the metal of your choice. Finally, click the middle of the 'Change Layer' button. The metal layer of the selected net should now be changed. Verify this by zooming in on the net until you can see the metal number.

Modules 17-18

There are no labs for these two modules.

Module 19: Verification

Module 19 contains fairly straightforward labs that teach how to perform various verification checks in the Innovus software. This includes design rules checking as well as checking connectivity. There is one optional step mentioned in which the lab manual asks the user to view a loop using the 3D viewer. In the Palmetto Cluster this cannot be done as there is no access to the software which is needed to run the 3D viewer within Innovus.

Module 20: Engineering Change Orders

Module 20 has yet another easy and straightforward lab. This lab involves using the eco route feature of Innovus and simply requires running a handful of commands.

Modules 21-22

There are no labs for modules 21 and 22.

Module 23: Innovus Database Access Commands

Similar to module 20, module 23 involves using a handful of commands. These commands will help with gathering information about the software and the design. Remember that when querying attributes for a singular cell use the singular function base_cell:*, rather than the plural (base_cells) as you would when querying multiple or all cells.

Module 24: Stylus Flow Generation

The final lab for this course, the flow generation involves creating a new flow and modifying some scripts. Towards the end of the lab, you must run the flowtool -reset function prior to trying to access the reports directory. This function can take a little while to complete running, so be patient with this step.

Resources

• Cadence Innovus Overview can be used to learn about the advantages or uses  of the Innovus software

Later on the lab will require you to save the version of the DTMF_CHIP you are working on. In order to save it you must currently have the top-level design open in the Innovus window. The window should look similar to the one seen below.

Module 4: Placing Pins

There are no labs corresponding to module 4.

Module 5: Bus Planning

Module 5's lab is fairly straightforward. Later into the lab there is a step which requires you to use the F3 key. Be sure to hold down the function key while doing so, otherwise the program will not recognize the simple pressing of F3.

Module 6: Interface Logic Models

The lab associated with module 6 is fairly straightforward and simply requires that you run a handful of commands. Remember that you must first write the ilm directory for both the tdsp_core and the arb designs before reading them into the top-level DTMF_CHIP design. Also make sure that the directories are named correctly.

Module 7-9

There are no labs corresponding to modules 7 through 9.

Resources

• Cadence Innovus Overview can be used to learn about the advantages or uses  of the Innovus software