Jarrett's Guides (Compiled)

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Using Cadence's learning maps, you can see the general order of how to approach Cadence's online courses. On page 2 of that document, you can see the PCB Design and Analysis map. Once you have downloaded all of the software needed (using the getting started page), you can start at the top of this learning map. Remember that you must be currently connected to the VPN in order to run the software. 

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Allegro Design Entry Using OrCAD Capture 

Requirements

General Notes

Module 1

On the Module 1 page, click "Database Downloads" (also located at the bottom of the page) and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, most likely called "20210420-bimai-02" and click "Extract all". Also, open up the "Lab PDF" in a new tab. See below.

Module 2

This module provides great information on getting started with the Capture CIS software. It covers everything regarding opening the correct software, setting the correct environment variables, opening projects, navigating your projects, and the basic UI functionalities of the software. Please note that when launching the Capture CIS 2022 software, you'll want to select "Allegro PCB Design CIS L" product choice. It has a different name than the "OrCAD Capture" option they mention in the videos for this module, but it's the same thing.

Another useful portion of this module is the slide showing the common shortcut keys. These will be extremely useful if you use this software frequently and want to be able to work a little more efficiently.

Other than this, the labs are what you're going to want to focus most of your energy to. The videos for each of the modules give in-detail information and the demo videos are nice for seeing things in action, but personally, I've found that the best way for me to learn using these Cadence training courses is to skim the videos for keywords and important info and then to jump right into the lab assignments.

The labs for Module 2 are really straightforward and just have you work through different navigations and setups for the software to get you ready to move onto more in-depth topics. If you get confused in this section or in any other sections, some common intricacies are covered in Nicholas's Guides.

Module 3

This module works through the different preferences that you can use to set up your software's environment in the way which works best for you. One of the important parts about this module is the video on the Title Block Tab, which is extremely for making sure all the right info is on your project if you're turning it in for some assignment. Other than that, I suggest paying attention to the "Creating a Design Template" demo video and then working on the labs, which will step you through the same process shown in the demo video for setting preferences and making your design template.

Note: In part 5, the lab says to simply add "\ram" to the end of the file path, which should be done, but first I would recommend going and creating the ram folder within the ftb folder in your file manager. Some computers may not automatically create the folder when a path which points to a file that does not exist is entered, and will prompt an error instead. 

Module 4

Module 4 introduces you to the concepts of libraries in Capture. Libraries are where are the parts that you may want to use will be stored, so it's important to understand this concept if you plan on making any sort of schematic designs with Capture. The most important sections of this module are the ones detailing how to copy parts from one library to another, as this will be a lot of help in creating any of your own libraries.

Additionally, understanding how to create your own parts is EXTREMELY important for any sort of schematic work. It's also key to understand the differences between homogeneous and heterogeneous parts: a homogeneous part is a part with ONE symbol defining it that contains either one part only or multiples of the same part, each with their own pins (single-section). A heterogeneous part has multiple, unidentical parts within a single package (multi-section). The differences between these two classifications becomes more clear if you follow through the videos and the demos for creating the two different types of parts.

The next important section of this module is the "Generating a Part from Imported Data" section, which basically describes how to use manufacturer information as a shortcut to create parts automatically. This sort of method will come up again for creating entire schematics from spreadsheet data.

Module 5

Module 5 brings together a lot of the previous information to show you how to begin creating your own schematics by hand. It'll cover a lot of the interfacing methods and UI options for schematic creation, as well as some tips and tricks to make this process quicker.

Module 5 also covers Design Rules Checks, which is one of the more important tools in the Capture software. This will allow you to automatically check your schematics and your work to ensure that everything is connected properly and is within your defined specs. It's super useful for double-checking work before you turn something in or move on to the next stage of a project.

Module 6

Module 6 is one of the modules where the Labs are key. Since most of the videos for this module cover technical processes like how-to's for creating schematics, it might be easier to just start on the labs right away and then reference the videos for help if you run into any trouble. The videos contain a lot of useful information on the specifics of how things work for this type of schematic creation -- it is very important to pay thorough attention to them in order to understand what each constraint manager page is used for and what properties they can control -- but the Labs are where you'll get the really useful practice of working through these examples on your own.

Module 7

Module 7 covers part properties for parts in schematics. Other than actually creating your schematic design, I feel like knowing how to manage the properties of your parts in your design is the next most important thing. From my experience in personal projects, I've found myself spending a majority of my time on Capture editing and changing around part properties, since these control the different values for components as well as their physical properties, which come into play a lot when you are creating a PCB off of one of your Capture schematics. This will also come in handy a ton when creating your Bill of Materials (BOM) for a project, since this will be created directly off of your part properties.

Pay attention to the labs regarding using spreadsheet information for part properties - this is a trick I wish I knew about when I was designing some of my own schematics, as it can cut down hours of time to minutes since using this skill will eliminate the need to manually change each part's properties.

Module 8

Module 8 covers creating hierarchical designs. Hierarchical just means that you have a design which contains sub-circuits consisting of other schematic designs. Think of it like how your computer may have a main design for the motherboard, but then sub-designs for each of the components connecting to the motherboard like the CPU and the RAM. Hierarchical designs are super important for modularizing your projects, especially if you repeatedly use certain sub-circuits in your designs or have a large schematic.

The other important section of this module is the section regarding netlists. A netlist is how you'll be able to create a PCB from your schematic, and if you have errors or mistakes in your part properties when you create your netlist, it may lead to lots of issues and errors down the road for your design process.

Module 9

Module 9 is just a simple summary of the topics covered in the course. Once you've gotten here, congratulations! You should be all done with this training course, and all you have left to do will be to complete the course evaluation and take your badge exam.

Badge Exam

Regarding the badge exam, don't worry! These are usually really easy if you did all of the labs for a course, and the exam will allow you to review your missed questions at the end and reattempt them as many times as necessary to get a passing score. They're all multiple choice questions and shouldn't take more than 10 minutes or so if you paid attention during the course.

Also, feel free to post your badge to your LinkedIn profile and connect with David Haeussler (https://www.linkedin.com/in/david-haeussler-559392). Once you've received your badge, let Dave know, and he will gladly repost your digital badge to help maximize its visibility. Don't miss out on this chance to amplify your badge's reach and showcase your accomplishm

Allegro Design Entry HDL Front-to-Back Flow

General Notes

Requirements

Introduction

This course introduces users to a different application using for creating schematics: the Design Entry HDL application. Similarly to the Capture CIS application, this software can be used to create schematics. The unique aspect about the Project Manager is that it can be used to launch both the schematic editor (Design Entry HDL) and the PCB Editor containing the PCB layout for the schematic.

Module 1 and Database Downloads

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab. See below.

Module 2: Getting Started With Design Entry HDL

The first learning module of this course covers the basics of operating the Design Entry HDL application. When first launching the Project Manager application, it will prompt you to select a product to use. Select the Allegro Venture PCB Designer Suite product, as seen in the image to the right. The lab for module two will also have you launch the PCB Editor application. If you have yet to launch and configure this software then it too will prompt you to select a product. For this choice select the Allegro Venture PCB Designer Suite option, once again as seen in the photos to the right. Be sure to check the Use As Default box, this way the program will not prompt you to choose a product each time it is launched. 


Module 3: Project Setup

This section covers the basic creation and setup of a Design Entry HDL project. The lab is fairly straightforward, however in step 5 of the "setting up a project" section, the lab mentions specifying the path to where the project will be stored. The lab says to simply add "\ram" to the end of the file path, which should be done, but first I would recommend going and creating the ram folder within the ftb folder in your file manager. Some computers may not automatically create the folder when a path which points to a file that does not exist is entered, and will prompt an error instead.

Module 4: Design Entry and Packaging

Module 4 covers part placement as well as other topics such as packaging, page management, and changing modes in the Design Entry HDL application. Each section of this module is very important as processes such as packaging are integral, especially when you start carrying the design over to the PCB Editor. Once again the lab does a great job walking through the material, however one issue that I encountered was that the application would get stuck while packaging at times during the back-annotation step. If it does this, simply restart the computer, re-open the schematic and run the packager again. Another important note is the material in lab 4-9. This lab covers switching to Windows Mode in the Design Entry HDL software. It is very important to keep the application in windows mode for the remainder of the lab as the rest of the lab manual is written assuming the user is still in windows mode. To ensure you are in windows mode, click tools, options, and under the General tab, ensure "Enable Pre-select Mode" and "Enable Windows Mode" are selected, as seen below.

Module 5: Hierarchical and Team Design

This module covers hierarchical design, a little bit of schematic entry and design, net listing, and creating a BOM. Since module 5 will have you creating some more schematics, it is very important to have the reference schematic pdf open to follow along. This is the schematic the lab wants you to create. This pdf can be found within the pdf folder in the ftb folder.

Module 6: Design Rules

Module 6 covers the constraint manager and all the different property tables which it contains. The lab is very straightforward for this section, but it is very important to pay thorough attention to the lecture section in order to understand what each constraint manager page is used for and what properties they can control.

Module 7: Rules-Driven Layout

Since this section finally covers carrying the design over from Design Entry HDL to the PCB Editor, it is important to ensure you have the PCB Editor application up and running. Lab 7-3 will have you run the auto-router in PCB Editor. This function automatically creates the connections between components on the PCB. If you are using the v22.1 PCB Editor, the auto-router will not work. To get around this, run the auto-router on the PCB Editor 17.4 application.

Module 8: Engineering Changes

The final learning module for this course, this section covers some design synchronization between Design Entry HDL and the PCB Editor. This will allow you to make changes in one program and update the other program. The module will also cover some basic project management, such as copying projects.

Allegro Design Entry HDL Basics

General Notes

Requirements

Introduction

This course builds on the schematic design entry concepts touched on in the Design Entry HDL Front-to-Back Flow course and introduces the Library Manager. Using the Library Manager allows users to create new parts to be used in a schematic as well as handle and explore libraries for a project. The modules for this course are very short, but it is still important to be thorough when going through the course as part development is integral to the design process. This course can be completed in its entirety using either the 17.4 or 22.1 software.

Module 1 and Database Downloads

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab. See below.

Module 2: Using Project Manager Design Flows

Serving as an introductory section, module 2 covers how to operate the project manager. First this module re-covers the Board Design flow and how to launch the Design Entry HDL application. For this part of the lab you will want to use the Allegro Venture PCB Designer Suite product if using the 22.1 software, or the Allegro Venture System Design Authoring product if using the 17.4 software. The second lab will cover something new: the library design flow. Before opening or creating a new project make sure the project manager product is set to Allegro Library Authoring (PCB Librarian) if using the 22.1 software or Allegro PCB Librarian XL for the 17.4 software.

Module 3: Setting Up a Library Project

Module 3 covers the setup process for a new library project as well as the part developer. To perform these tasks you will need to be using one of the library authoring or librarian products mentioned in the module 2 section, depending on which software edition you are using.

Module 4: The Symbol View

This module is incredibly important as it covers the symbol view of a new schematic symbol. The lab will cover the creation of the symbol view, which involves editing the pins, pin placement, labeling, etc. of the schematic symbol. This will also cover some basics of using the part developer, the application used to create new schematic symbols.

Module 5: The Chips View

Similar to module 4, this module is incredibly important as it ties into the part creation process. This time the lab will cover pin mapping and package definition. This step is integral if you plan on bringing your schematic over to the PCB Editor as your part will need a PCB Footprint (package definition) and will need to have pins correlating to the I/O of the package. For more information on IC packages refer to the resources entry of this guide section.

Module 6: The Part Table View

The final step in the part creation process, this module covers assigning properties to your new part. The lab also covers the final necessary information relating to the Part Developer basics.

Module 7: Testing the Part

For the second lab in this module you will need to have access to the PCB Editor software. Either the 22.1 or 17.4 software should work for this so it is up to your discretion which to choose. If the PCB Editor prompts you to select a product, make sure you select the Allegro PCB Venture option. The lab does a good job of walking you through what is needed to complete the task at hand in the PCB Editor, but for more information on operating the PCB Editor application, refer to the OrCAD Crash Courses section of this guide page.

Module 8: More Part Building

The final module covering the use of the Part Developer tool, module 8 covers some semantics of the tool's use such as copying parts and opening multiple parts. Module 8 also covers split and asymmetric parts and how they are handled or created in the Part Developer.

Module 9: Setting Up a Design Project

Module 9 dives back into using the Design Entry HDL application. This means you will need to switch back to the Allegro Venture PCB Designer Suite product if using the 22.1 software, or the Allegro Venture System Design Authoring product on the 17.4 software.

Module 10: Design Entry and Packaging

The labs for this module cover some design entry and creation. This is somewhat redundant as nearly all this material was covered in the Allegro Design Entry Using OrCAD Capture course, however, I would highly recommend still thoroughly following along with the lab as it is good review and practice. This module's lab is also taught using the standard mode, as opposed to the windowed mode covered in the previous course. Remember always to choose a PACK_TYPE (as seen below choosing the SOIC option) option or VALUE option (for a discrete component) when adding parts, even when there is just one option. Failure to make a selection for one of these categories will prompt an error when trying to save the project.

Module 11: Engineering Changes

Once again somewhat redundant, this module covers basic information such as copying projects, editing copied projects as well as repackaging. Yet again, this is a great opportunity to practice skills learned in earlier courses.

Allergo PCB Editor Basic Techniques

General Notes

Requirements

Module 1 and Database Downloads

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab. See below.

Module 2

For this module, once you open the PCB Editor, choose the product "Allegro PCB Venture," as this is the one we have access to due to the licensing. Other than that, this module is fairly straightforward.

Module 3

It is recommended to make sure that you have the Find, Options, Visibility, and Command windows open. To do this, go to view, windows, and click each of these options until they have a blue checkmark next to them. In lab 3-2, at part 7, when you press the Tab key, you should see the U3 device attach to your pointer like this (seen below).

Module 4

In this module, you learn about the PCB Editor Initialization. Using the different ways to set up the user interface, you change the font sizes, change windows, and learn how to assign tasks to certain keys with the editor command window. Lots of visual diagrams are provided to assist you in following the labs.

Module 5

This module is fairly basic, as the guide describes the steps in detail. You create the PAD STACKS for the PCB.

Module 6

In this module, you learn all about package symbols. In lab 6-1, you will setup your first 16-pin DIP with package symbol wizard. Shown below (on the left) is what it should look like after you finish the lab. 

Shown below (on the right) should be the final result of creating the SOIC 16. 

For all of the labs using the 3D canvas, just make sure all of the contact points look lined up once you have finished following the directions in the lab. 

Module 7

In this module, you learn how to create the outline of a board. 

In part 7-1, you will need to add chamfers to your design, and at one point, you will need to add the dimension for the angle and length of the chamfer (which we found to be a bit tricky). Make sure you select Dimension/Drafting > Dimension Environment before you right click otherwise, the chamfer leader option will not be present. 

Module 8

First, when you go to the Project Manager application, use the "Allegro PCB Designer Suite" product instead of what the lab book tells you to use, as "Allegro PCB Designer (Layout)" is not an option due to our licensing. The main important part of this module is making sure you do the correct part of the module corresponding to what you've done earlier in the course. Also, when using the System Capture Application, pick any product to see what works. (Try to pick one that has a similar name to that given in the lab book).

Module 9

For this module you will learn how to edit specific properties for pins and nets along with set constraints. There are no major tips or guides for this section as the instructions are very clear and with the knowledge up to this point you have everything you need to complete it. 

Module 10

In module 10, you work on placing components and all the details that go along with them. During lab 10-2, you will incrementally reference the RefDes of the devices on the board. The first device you need to change is the J* in the bottom left, which should become J1. During this lab, you will begin placing parts, specifically U1, 2, 3, and 4. While placing these, you will see a bunch of light blue lines in the picture, and it can get quite messy. These are rat's nests or unconnected pins, which you will learn more about when you route connections. The red and green "A" looking icons allow you to turn on and off the rat's nest. This will just make your board easier to look at without all the lines.

The rest of the lab is fairly straightforward, but the hard part will come with a lot of practicing with the moving, rotating, and deleting components. You will be given at many points reference pictures for how your board should look at certain points. I highly recommend taking the time and moving these components to the places you see in the most effective and fastest ways possible. That means rotating at user-picked points and using ctrl-click on the components you want to move.

Below is an example of what your board might look like at the end of the lab.

Module 11

Module 11 is super  quick and really easy to follow. There is not much to go over this and it is very self-explanatory. 

Module 12

Module 12 is where we can learn about routing which is how we actually connect the pins on the board to other components. There are many options for doing this with a variety of settings for how we organize the board to be as clear and realistic as possible. Shown below is how the GND and VCC planes should look after completing 12-4.

Module 13

For this module, you will need the 17.4 versions of the application. As stated before, this is due to licensing issues. If you only have the 22.1 version downloaded, go to the getting started page of this website and follow the directions to download the 17.4 version.

Module 14 & 15

We did not find any big issues with this section of the course. Just follow the directions very closely, and you should be fine.

As a general tip for the course, if you feel you don't really remember parts of the course or have a bunch of errors in your files, it may be beneficial to go back through certain sections of the course to help you remember how to use the software correctly, and this will likely help you on the badge exam as well.

OrCAD Capture Constraint Manager PCB Flow

General Notes

Requirements

Resources

Introduction

This course covers bringing a design over from the OrCAD Capture schematic editor to the PCB Editor. This will cover many aspects of the design process and in particular the use of the constraint manager to set parameters for the PCB layout. Please note that at the moment Cadence only offers the 17.4 version of this course, but you can follow along using the 22.1 Capture software just fine. However you will need access to both the 22.1 and 17.4 PCB Editor if you choose to use the 22.1 Capture software. This guide will cover some of the differences between the 22.1 and 17.4 software as they show up in the course. (Recommended to just use the 17.4 software)

Module 1 and Database Downloads

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab. See below.

Module 2

The second module covers some basics of operating the constraint manager such as adding properties and creating classes. The first lab will involve modifying or adding some environment variables. The easiest way to do this in my opinion is to simply launch the environment variable page by entering Environment Variables into the windows search bar, then selecting the "Edit the system environment variables" option. This will open a new system properties window, where at the bottom you will see a button which says Environment Variables... (Forewarning, the pictues given by the lab book are a bit outdated so the buttons are not going to be where shown, but they will still all be in the same windows somewhere, you just have to find them.) Click the button to edit your environment variables. From here add your CDS_SITE and HOME variables but be sure to save any existing environment variables of the same name by changing the name beforehand.

When the lab book tells you to choose the product "OrCAD PCB Designer Professional," actually choose the "Allegro PCD Design CIS L," as we do not have their option available. After this, the lab will walk you through using the constraint manager. Some small details to note: first when the lab has you using the differential pair automatic setup tool, on the 22.1 software if you simply enter _P and _N into the +Filter and -Filter fields, pressing Enter will automatically create the differential pair, instead of populating the fields as the lab has you do. Finally when the lab has you creating net classes, there is a step involving creating a class with the BNC2, BNC3, OUTA, and OUTB nets. If you are using the 22.1 software, do not worry about looking for the OUTA and OUTB nets as they are included in the BNC2 and BNC3 nets, thus you only need to include the two BNC nets in the net class.

Module 3

Module 3 involves the transition from design entry in Capture CIS to circuit board layout using the PCB Editor. If using the 22.1 Capture CIS software, you will find the *.brd file in the project manager within the layout folder. To launch the PCB Editor you can either double click on the *.brd file or you can right click the file then select Launch PCB Editor. When the PCB Editor asks you to choose a product, choose "Allegro PCB Venture", instead of "Allegro PCB Designer", as we do not have access to that option. In lab 3-4 for this section you will be asked to use the automatic router in the PCB Editor. If you have already done the Allegro Design Entry HDL Front-to-Back Flow course then you should be familiar with the issue that arises from this. Since we do not yet have access to the 22.1 routing license, you must use the 17.4 software to run the auto router. For instructions on how to install the 17.4 software, refer to the getting started section of this website. Once this software has been installed, you can simply open the *.brd file you were working on in the 17.4 software, follow the lab instructions on running the auto router, then save the changes made to the file and reopen it in the 22.1 software. One of the biggest differences between the 22.1 and 17.4 software that shows up in the lab is the design synchronization tool. In the 22.1 software there is no one "Design Sync" button as there is in the 17.4 edition. Instead there are two options. If you have made changes in the schematic editor, then choose Update Layout to sync the PCB design. If you have made changes in the PCB Editor then choose the Update Schematic to sync the schematic design. Aside from this the update layout and update schematic windows should look very similar to the design sync window from the 17.4 software and should be easy to follow along with.

3-1

In the beginning of this lab, you have to navigate using the browse button to where the Cadence software is downloaded on your computer. Normally, they are in the "This PC">"OS (C)">"Cadence">"SPB_17.4" directory. If not, search a cadence app in the search window on the bottom left of your computer, left click on the selection and choose "Open File Location," and you should be able to see where the data is downloaded.

Module 4: Engineering Changes

The final module covers some more basics of design synchronization such as synchronizing changes to the constraint manager and regenerating a netlist. These labs will involve using the design sync tool as well as the auto router, so be sure to read the module 3 guide to understand how to deal with the issues arising from these tools. One other issue you may encounter in this lab is netlisting errors. If the netlist fails to generate then you will see the error message shown below (to the left). If this happens then open the session log window by choosing View > Session Log Window from the pull down menu. The session log will print out the errors the netlist generator is encountering, an example of which can be seen below (to the right). In this case there was a duplicate reference designation in the resistor 'R6', which could be fixed by editing the resistor properties and changing the resistor's name.

Allergo PCB Editor Intermediate Techniques v22.1

General Notes

Requirements

Module 1 and Database Downloads

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab.

Module 2

In lab 2, they actually give you a little bit of a task where you use the Display-Measure command and change the DFA Constraints to match the DRC error picture in the Lab. You will actually be changing the constraint value for the Vertical and Horizontal air gap so it is important to know what the initial is to find estimate a value to give you the desired results.

Module 3

In the first lab of this module, you go through a bunch of different .brd files to practice editing the routing of wires. Most of them are very explanatory and if you have any trouble just restart from when you open a certain .brd file and you should be good to go.

Module 9

In lab 1 and 2 of this module, the main part I got stuck on is routing the differential pairs. This would be easy, but you need to route some of the connections on the int layers of the board using vias. To do this, go ahead and route as many of the connections as you can before you need to cross some of them. (Seen below in picture to the left). Once you are done with this, go ahead and change the alternate layer in the options tab to "Int 1", then, right click to "Via Pattern" and select whatever via pattern works best with your current wire direction. Then right click and choose "Add Via", then you can route across the other wires. Now, right click again and choose "Via Pattern" and then "Add Via" and finish the wiring to the destination differential pair. (Seen below in picture to the right).

In addition to this, in the end of lab 1, you are tasked to change the Max Uncoupled Length to get rid of the DRC's. If you hover your cursor over the DRC error it tells you the actual value which easily allows you to change the Max Uncoupled Length to get rid of the DRC.

Module 12

For this module, you are required to create .txt files that when run using extracta, display the correct values told by the lab to retrieve from the file. To do this, it is recommended to watch all of the lecture videos all the way through. This gives you a good sense of how to write these files. 

The way I recommend writing these files is by going into tools, reports, NEW/EDIT, then use this to start off with all the components needed. Once you save this file, go to it and make any needed changes to the code. 

Below, you can see how I wrote the code to solve lab 1. First, for the group, there are probably multiple different options that would work but I chose Composite_Pad. Then I selected "NET_NAME," "PIN_NUMBER," and "REFDES," as these are the three requested by the lab. I then saved this file, and went into Notepad on windows to edit it, adding the " = '' " next to the NET_NAME line. This makes it so the report only includes those pins that are unused.

Allegro System Capture

General Notes

Requirements

Introduction

This course introduces yet another schematic design application, the System Capture app. The unique aspect about this app is that it allows for users to import designs or libraries from other applications such as DE-HDL and OrCAD Capture. System Capture also gives users access to parts from external libraries. Using the System Capture software is fairly similar to using the previously discussed schematic design apps and this course will give a similar overview covering placing parts, drawing wires, generating netlists, etc... 

Module 1

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab.

Module 2

The first learning module of the course gives a general overview of creating and opening projects as well as the user interface of the schematic editor. The first lab will require you to the set the CDS_SITE system variable. The OrCAD Capture Constraint Manager PCB Flow section of this guide page has some images and a short description to guide you through modifying system variables. Setting the CDS_SITE variable to the proper directory is important as this specifies different setup and layout settings and contains different libraries you  will need access to. Once you get around to launching the System Capture application you will be prompted to select a product. If you are using the 22.1 software use the Allegro System Capture Venture product. If you are using the 17.4 software then choose the PCB Designer product. When you first open or create a project try to use View>Panels>Unified Search to open the Unified Search window. This window may prompt you to sign in. You can sign in here to access the SamacSys tab which allows you to search for parts from external libraries. Make sure to uncheck the Ultra Librarian box when signing in. Additionally you can skip the sign in if you only need to search for or place parts from local libraries. 

Module 3

The third module covers creating a new project and tailoring project settings. This includes graphics in the schematic editor such as modifying how the grid is displayed and changing the page setup as well as editing user preferences. This section is fairly straightforward but is critical to getting started. 

Module 4

Module 4 dives into editing or creating libraries and library parts. It is important to note that when you are creating a library, the path name to the library does not contain any spaces in it as this will cause an error. Also keep in mind that if you change any directory names within the path that are also contained in the CDS_SITE path, the CDS_SITE variable will not update. Thus if you change a path name make sure to update the CDS_SITE variable as well. 

Module 5

This module goes over the basics of schematic design in the System Capture software. This includes placing parts, wires, buses, bus taps, etc. Module 5 also introduces Version Control, a unique feature which allows users to view and switch to previous versions of a design. If you encounter any issues when trying to commit a new version to the version history the most likely culprit is the Part Manager. Before committing the part manager may need to be updated. To do this go to Tools>Part Manager then in the part manager window choose Update. This should solve the issue, however if there are parts which need to be manually synced this can be more challenging. This issue will be discussed in the module 8 section of this guide. 

Module 6

Module 6 covers hierarchical designs as well as importing design files from other Cadence products and importing user-created libraries. The lab of this section will have you use the Project Manager and DE-HDL software. If you have never launched these products before then choose the Allegro Venture PCB Designer Suite product regardless of the software edition you are using.

Module 7

This module introduces the constraint manager once again. Using the constraint manager in System Capture is very similar to using it in OrCAD Capture or DE-HDL, so this module should seem pretty familiar at this point. Make sure to still be thorough when going through the labs as the changes made in the constraint manager are important for when the design is transferred to the PCB Editor.

Module 8

The final learning module covers transferring the design from the schematic editor to the PCB Editor as well as back annotating the schematic from the PCB Editor. This module's labs gave me quite a bit of issues, the first of which involved the part manager again. The first lab involves generating a netlist, however an error was prompted when trying to do this due to the part manager not being updated. However this time the part manager could not be auto updated because it needed a part to be manually updated. For this instance the part that needed updating was the RAM TC55B4257 part. To manually update a part there are two ways to go about it. First you can open the part manager and select Details. From here filter the list of parts by Manual Sync and then select the Select a part for replacement button for the part that needs to be manually synced. In my case this didn't work so I chose the second way to solve this issue. I simply used the unified search to find a library version of the chip I needed and replaced all the parts that needed to be manually synced.

 

The second issue involved placing parts in the PCB Editor. For some reason the DAAMP parts could not be placed as one group in a predetermined pattern as the lab said they could be. The workaround for this is easy. The lab manual has a picture of the layout so the parts can be placed manually by using the image as a guide for which parts to place and where to place them. Later the lab asks you to display rats nest lines using cross referencing between the two programs. This may cause some trouble so to display the rats nest lines using only the PCB Editor you can start by clicking Display>Show Rats>All. Next click Display>Blank Rats>All. After this open the constraint manager by choosing Setup>Constraints>Constraint Manager. Once open simply click on whatever net you'd like to display it's rats nest lines. The final issue is one that you may have encountered already. When the lab asks you to auto route the PCB design, this must be done in the 17.4 software as we do not have access to the auto routing license on the 22.1 software. For detailed instructions on how to do this refer to the Allegro Design Entry HDL Front-to-Back Flow section of this guide page. 

Resources

Analog Simulation with PSpice Using System Capture

General Notes

Requirements

Introduction

This course introduces some of the simulation abilities of the Cadence PSpice library and PSpice applications. It is important to have completed the System Capture course before beginning this one as you will need to know how to use the System Capture software. This course is only offered for the 17.4 software, but can be followed along with using the 22.1 software edition. 

Module 1 and Database Downloads

Module 1 of the course simply contains an overview of what the course will cover. It is still important to read over this and gather an understanding of what you will be learning. Before starting the course you should head to the Database Downloads module of the course. On the Module 1 page, click "Database Downloads" and save the folder "Lab Database" to a location on your computer. I recommend making this folder easy to access as you will be navigating to it a lot throughout the course. Right-click on this folder, and click "Extract all". Also, open up the "Lab PDF" in a new tab.

Module 2

This first module covers setting up System Capture to use the PSpice products as well as how to place PSpice capable parts. When you first launch System Capture you will likely need to change the product you are using. This can be done by going to File>Change Product then selecting the Allegro System Capture Venture product and checking the PSpice checkbox. Once System Capture has been configured and a project is opened you will need to include the PSpice libraries. If you are having trouble doing this, I would recommend opening the project's CDS.lib file using the notebook application. This file can be found within the project directory. Once this has been opened insert the statement INCLUDE "C:\Cadence\SPB_22.1\share\canvaslibrary\pspice\canvaspsp_cds.lib" which will include the PSpice libraries. Please note that the path listed above may very and is simply the path to the canvaspsp_cds.lib file which should have appeared when extracting the pspicecanvaslib.exe file. Once this statement has been added save the file and restart System Capture. All the PSpice libraries should now be listed in the Available Libraries section of the preferences page. If you encounter any issues while placing parts during the lab be sure to select parts from the Library tab of the Unified Search window rather than the myparts tab. 

Module 3

Module 3 teaches the first basic analysis tool offered by the PSpice product: a DC Bias Point analysis. This analysis will calculate the DC Bias Point based on any DC sources and initial conditions. The lab for this section is short and straightforward, just make sure that System Capture has been set up properly to avoid any issues. 

Module 4

The second analysis type, DC Sweep, will calculate the steady-state voltages and currents when sweeping a source, model parameter, global parameter, etc. As with the previous module this lab is very short and straightforward. Once again refer to the setup process for any issues accessing PSpice products in System Capture. 

Module 5

Another capability of the PSpice simulator, an AC Sweep analysis will find the small signal response when sweeping an AC source over a range of frequencies. This lab will require you to create a new file, do not forget to add the PSpice libraries to the cds.lib file in order to access PSpice parts. Refer to module 2 for instructions on how to do this. 

Module 6

PSpice can also be used to simulate a circuit from an ASCII netlist file. This lab will use the PSpice AD product so be sure you have access to this program. Within the PSpice AD program you will need to plot a function. To do this first select the function from the Functions window (in this case the DB() function) then select the signal you would like to plot from the Simulation Output Variables window. 

Module 7

This next analysis method will measure the circuit's response in the time domain. In this lab I had some troubles copying the project. If you encounter these same issues I would recommend simply using the original file to complete the lab, or restarting System Capture and trying to re-copy the project. 

Module 8

This module will cover some errors that may be encountered during the simulation process, some of which you may have already seen. In one of the later labs you will be asked to place a LIMIT part to solve an error. When I tried to do this I encountered the error to the right which would not allow me to place the part even though the PSpice libraries were included in the project. If you run into this issue as well I would recommend manually adding the libraries by adding the same include statement mentioned in module 2 to the project's CDS.lib file. 

Module 9

This module covers creating and simulating several different types of transformers. As always, remember to include the PSpice libraries in each new project you create in order to access the proper parts and simulation models necessary. 

Module 10

Module 10 introduces a new kind of analysis, parametric, which involves using a parameter and viewing its effect on a circuit. This module only includes one lab which is fairly straightforward. 

Module 11

This module covers editing the PSpice models of parts. You will need to use the PSpice Model Editor program for these labs so be sure that it is installed and operating on your computer. The first lab involves editing an existing PSpice model and viewing the behavior of the circuit before and after the edits. To edit a model you must select a part, right-click on the part, then choose Edit Model from the bottom of the list. Refer to the figure for Module 14: Monte Carlo Analysis for a depiction of where to find this option. The second lab will involve the creation of a PSpice model. This simply requires you to input some values into the model editor then place the part in a schematic. The final lab can be somewhat challenging, likely due to an issue with the pre-designed circuit from the lab database. If you encounter the error sequence shown to the left while trying to simulate your circuit, the best course of action in my opinion is to simply remake the circuit. This is unfortunately a very tedious process, but it is the best way to get the simulation to work. 

Below this module paragraph, I have included images of the working circuit as well as the configuration for the simulation. For the circuit, there are a couple things to note. First, the voltage source V2 is a vsrc part for which you will need to assign the TRAN, AC and DC properties. Second, the part you see labeled Advanced Analysis Properties is a variables part from the pspice_elem library. Most of the properties will remain as the default but there are a few that need to be changed or added, so be sure to reference the below schematic and assign all the properties accordingly. Finally the reference designators and net names are very important to the simulation so copy them exactly as you see them below. For the simulation, the settings that need to be changed are pictured below, the rest of the settings will use the default. For the Stimulus page you will need to add the rf_amp.stl file. This file can be found using the following path: C:WhereverYourSysCapFileIsStored\SysCapPSpice\rf_amp\logic\rf_amp\worklib\rf_amp\psp_sim_1\profiles\rf_amp.stl. This can be added using the same process as you would add the STN0214.lib file to the Library section of the simulation profile. At this point the simulation should complete successfully, though it is important to note that the graph may not look exactly as it does in the lab manual, likely due to the polarity of some capacitors. I would not worry too much about this issue as the important part is generating a working simulation with an imported PSpice part. 

Module 12

Module 12 introduces some aspects of hierarchical design, involving creating a circuit, designating it as a subcircuit and using it in another project. The first lab of this module is fairly straightforward, but the second requires some patience. First, when creating the new project, if there is a warning in the violation window regarding a syntax error in the CDS.lib file, double check the file to make sure the INCLUDE statement for the PSpice libraries and the DEFINE statement for the buffer_lib library are on different lines. When placing your buffer part it will appear in the MyParts window. If it does not show up be patient and wait for the MyParts window to load. Since this window needs to load in 28,000+ parts it may take a while to load in the buffer part, so wait for the window to say 28k+ at the top before searching for the part. 

Module 13

This module teaches how to perform a temperature analysis, which will calculate the circuit's response to different temperatures. This module only involves one lab. For this lab be sure to place the voltage probe after creating the simulation profile otherwise the probe will have no effect. 

Module 14

A Monte Carlo analysis randomly changes the values of certain circuit components and calculates the circuit's response to the changes. This lab will cover creating a circuit then running a Monte Carlo analysis on the circuit. If you choose to construct the circuit yourself, be sure to update the part manager before simulating the circuit. In order to edit the PSpice model of a component, right click then select Edit Model which will be found at the bottom of the right mouse clicker menu. This will open the PSpice Model Editor as seen to the right. 

Module 15

Module 15 covers using hierarchical blocks in a circuit and simulating said circuit. The labs involve building and simulating several circuits. In lab 15-2, if you are having trouble generating or finding the proper signals, I would recommend rebuilding and re-importing the clipper circuit as there may be some issues with the original. In the same lab the manual says to type in some functions and signals in the Trace Expression field. I would instead recommend clicking and choosing the functions and signals. This can be done by first selecting DB() from the Functions or Macros field, then choosing V(OUT) from the Simulation Output Variables field. Then repeat this for V(MID). 

Module 16

The 16th module goes over simulating circuits with analog signals. This module contains four short labs. These labs are fairly straightforward, but as always remember to add the proper libraries to the project. When doing the labs be sure to add the voltage probes to the circuit after creating the simulation profile, otherwise the probes will be removed. Also note that the simulation results from labs 16-1 and 16-2 should look the same. 

Module 17

This module covers the process of simulating circuits that contain digital components. When placing parts for the circuit you may come across several pop-ups that are not mentioned in the lab. When placing the $D_HI and $D_LO parts the program may prompt you to select a voltage. I used 5V and 0V, respectively, which seemed to work fine. It should also be noted that the manual says to use the parts from the source library, however I used the parts from the dataconv library which seemed to have no effect.  

Later when placing the digstim1 part the program may prompt an error saying "implementation property missing", as seen to the right. At this point simply enter the name for the part mentioned in the manual then press ok to open the stimulus editor. Finally, in the simulation window the lab manual says to display the "DSTIM1:OUT" signal, however it may be difficult to find this value. Instead refer to your schematic and find the net name of the net shown below, then select this net as a trace in the simulation window. In my case the signal was named _N1, but yours may be different. 

Module 18

As the title describes, this module involves simulating a circuit that contains both analog and digital elements. When performing these simulations the digital and analog signals will be shown side-by-side. This lab only has one part. 

Module 19

Module 19 covers creating performance analysis graphs as well as generating functions to analyze a simulation. The second and third labs for this module require the use of the buffer project created earlier in the course. If you have lost this project or have modified it in any way, refer to the images below for the setup. When setting up the circuit make sure pin 2 for both capacitors is on top and be sure to flip the LF411 part horizontally when placing it (While placing the part right click then choose horizontal). The negative symbol should be on top and the positive symbol on the bottom. To set up the simulation, choose Time Domain (Transient), set the Run To Time as 5us and the Maximum Step Size to .01ns. Next check the Parametric Sweep box, choose Global Parameter, setting the parameter name as CVAL and give the sweep a start value of 100p, an end value of 700p, and an increment of 25p. 

Module 20

Module 20 offers a way to analyze the noise of certain circuit elements. This is another short and succinct module plus lab, but as always pay close attention and be sure to follow along with the lab. 

Resources

Website where the STN0214 part can be downloaded from

Allegro PCB Router Basics

General Notes

Requirements

Introduction

In this course you learn how to use a different program that allows you another way of routing your designs from the PCB Editor 17.4. This is directly connected to the PCB Router 17.4 program and you can go back and forth. I highly suggest taking notes for the badge exam because there are a lot of questions where you will need to select multiple answers for a singular question. Check the Notes tab when you watch the lectures to help you get more detailed explanations. 

Module 3

For this module in Lab 3-1 you will look at a report for the Design File where you have to find specific piece of information about the design. I have provided a basic outline for each part to help you make sure you are looking at the correct pieces of information in the design file

Wiring Paths

The VD Bus

4-mil Clearance

In lab 3-4 you learn to select specific parts and nets to route and the only real ambiguous part for beginners is what the two I/O connectors are. I have provided a image of the two connectors to help make sure you are on track while following this lab.

Module 4

In this module you learn how to analyze specific routing results. In the lab you will be given two different example cases where you need have look at key indicators  for the routing to determine answer for the questions asked in the lab. Make sure to watch the lecture videos and take good notes for what to look for and what you want ideally for your route status reports.

Module 5

In this module you start routing and learning about vias and it is very straight forward to follow but I wanted to provide an image for what a successful route with a via to the highlighted pins looks like 

Module 8

Module 8 includes a lot of practice with creating do files, list commands. It also includes a lot of practice trying to set up these things without looking at the solutions.

Using Palmetto Cluster

Connecting to the Palmetto Cluster 

Once you have been set up with access to the Palmetto Cluster (using the instructions from the Getting Started page) it is time to get started with using the Cluster. There are three easy ways to connect to the Cluster in my opinion. You can access a virtual machine on the OnDemand website by clicking on Interactive Apps > Palmetto Desktop then choosing settings and launching a session. I typically use 15GB and 4 Cores, but these numbers will obviously vary based on what you are trying to do. This is likely the easiest way to connect. 

Another way to access the cluster via the OnDemand website is to open a terminal session. This can be done by choosing Clusters > Palmetto Shell Access. Once the terminal has been opened you will need to enter a command to start an interactive session and launch the Cadence applications. In the terminal, enter "qsub -I -l select=1:ncpus=(number of cpus you want):mem=(GB of memory you need)gb,walltime=hr:min:sec". Look to the images below for an example. Once the session has begun you can enter a couple commands to load or view programs. Enter "module avail" to get a list of all available programs on the cluster. Enter "module avail cadence" to view all the accessible cadence programs that can be run. Finally to load a program, for example the Xcelium 22 software, enter "module load cadence/Xcelium/22". Refer to the module avail command to view the names of other cadence apps and how they can be launched. To end the interactive session enter exit. 

The final way I will recommend connecting is via ssh. This is easiest if you already have a virtual machine set up on your computer, or if you already run linux or mac. This can be done by opening a terminal session and entering "ssh username@login.palmetto.clemson.edu". After this you will be prompted to enter your Clemson password as well as a duo option. Once you've begun the ssh session you will need to follow the same steps as described above to start an interactive session using the qsub command. 

Transferring Files

If you need to transfer files to the Palmetto cluster, there are once again several options to do so. For downloading files you can use the OnDemand virtual machine, however if you have files on your computer that need to be on the Cluster there are several ways to transfer them. On the OnDemand website, click on Files > Home Directory. From here this will take you to a file management screen where you can transfer files from the Cluster to your computer or vice versa. 

If you operate on Linux or mac (or connect to the Cluster via ssh) then you can open a terminal session and use secure file transfer to send files to your Cluster profile. To do this, find the folder to send, then enter the command scp filename username@xfer01-ext.palmetto.clemson.edu:/home/username/destination. After this is entered you will be prompted to enter your password and choose a duo option. Once this is done the program will confirm the file has been transferred and return you to your home terminal. 

C++ Language Fundamentals for Design and Verification

Requirements: 

General Notes:

Module 1

Aside from the normal PDF downloads necessary for every course, this lab's database also comes in a compressed format. The instructions to uncompress them assume command line knowledge -- here's a more detailed step-by-step guide to uncompressing the downloaded file:

2. Open your system's terminal (this can be done through the "terminal" application or through other apps with integrated terminals such as VSCode)

3. Navigate to your Downloads folder


4. Once you're in the proper directory, follow the instructions on the site (Note: I didn't need the "uncompress <Lab>.tar.Z" step when uncompressing the lab database, though this may vary from system to system)

Module 2

This module is a fairly straightforward introduction to object-oriented programming concepts and their respective syntactical elements in C++. It also explains some of the differences between C and C++. I would recommend paying close attention to the concepts in this module if you are new to the concept of object-oriented programming, but for those with prior experience, the most important parts will be the syntactical implementations of these concepts. 

The lab for this section is simply an intellectual exercise -- it doesn't require you to actually write any code. Use it to test your knowledge of object-oriented concepts. 

Module 3

This module serves as an introduction for C++ the language. It covers basic I/O, declarations and scope, members access specifiers, the instance pointer "this," and the new and delete operators. 

Some of the I/O terminology can get confusing if you're only used to C syntax, but luckily C's printf and scanf are still accessible in C++ for those adjusting. The concept of flushing is also mentioned but not explained, but there are plenty of outside resources on it, such as this one. The scope resolution operator mentioned is :: (two colons), as seen in the example for scope resolution. If :: is put without anything before it it defaults to global.

The concept of friend functions is also mentioned here, and will be discussed further in module 8. All friend functions must be declared within the class with the friend prefix (though no function definition is required), and then any function named that name will be able to access protected and private variables. Though it's not explicitly spelled out, you will learn in later modules that the difference between protected and private is whether subclass member functions can access the region.

The new and delete operators are very similar to malloc and free, though there are some differences which are covered here. 

The concept of pass-by-reference also doesn't exist in regular C, but will be explained further in module 5.

The lab for this module is fairly straightforward. Feel free to reference back to the lecture PDF for terminology. 

Module 4

This module introduces the concepts of constructors and destructors in C++. The concepts of overloading and default constructors are also introduced because of this. If you're unfamiliar with how stack and heap memory actually work in C and C++, it would likely be good to review that before going into this module. 

Similarly, the concepts of pass by reference and lvalue and rvalue expressions will not be fully introduced in module 5. For those who don't already have a background in C++, skipping forwards to learn a bit about these concepts before coming back could be prudent. I found that I myself did not fully understand the contents of modules 4 and 3 before going on to module 5 and then coming back to them.

The lab for this module is again fairly straightforward, especially as there are no requirements for class variables in dynamically allocated memory.

Module 5

This module finally introduces aliases and reference variables. These concepts are very important for understanding both the previous and next modules, so paying close attention to the nuances is imperative. One particular nuance which this module does a good job of hammering in is that C++ treats named rvalue expressions as lvalue. 

It should be noted that like the * operator, the & operator can be affixed to both the end of the type and the beginning of the variable name (for example, int& myIntRef and int &myIntRef are identical statements). However, the syntax presented in the course is preferred due to both * and & binding closer to variable names than to type declarations (for example, int* ptr1, ptr2; would declare ptr1 as a pointer to an int, and ptr2 as a regular integer.)

It should be noted that almost no actual modern language is considered pass-by-reference. C++ allows the operation, but the standard passing of a normal object into a function still passes only a value. When learning other languages and how they pass a "reference" of the object to the function upon calling it, it is important to note that this actually means that they are likely passing in a value of a pointer or similar.

The lab for this module is again fairly straightforward.

Module 6

This module discusses functions, and how to best use them to optimize program reliability and performance. In doing so, it covers argument passing, overloading, const/volatile modifiers, and static variables. 

This module also seems to repeat some content from previous modules, which may be good for review but can be skipped if you're already familiar with the content. 

The concepts of const and volatile modifiers are introduced in this module. It should be noted that in the slide covering cost/volatile qualified functions, the square brackets indicate optional inclusion (Only a const [volatile] function can act on a const object, meaning a const function or a const volatile function).

The concept of functors is also introduced, and while the lecture on functors can be a bit confusing, they essentially allow the use of an object as a function by overloading the operator() method. A good resource on functors can be found here. Lambda expressions are a special type of functor defined at the point of instantiation, and are typically used for quick in-line function declarations. The lectures go into a lot of detail about the specifics of lambda expressions, but it's ok to just go over the basics and then return to the slides if the need arises for further specific knowledge.

The lab for this module is again fairly straightforward. Here's a good resource on enumerated types if you're unfamiliar with them (or skip to the next module's reference guide).

Module 7

This module covers type conversions, both explicit and implicit. 

The quick reference guide to C++ types at the beginning of the lecture is very helpful to reference throughout the course. In general, this module contains many tables and reference sheets which are very good to keep bookmarked for future reference.

The overview of type checking and some of the differences in type checking between C and C++ is very helpful, though if you ran your C code using a C++ compiler you may already be used to most of these standards. 

The lab for this module is more of an experiment, and allows you to learn the nuances of the reinterpret_cast operator. 

Module 8

This module covers operator overloading and best practices, as well as friend operators.

The basic concepts of each of these ideas is fairly simple, though the lectures go into a lot of semantic detail with many technical examples to flesh these ideas out. We also return to the concept of functors with this new knowledge, which helps to solidify the concepts learned in previous modules. 

There are a couple of useful tables and reference guides in this module as well, with the last guideline for operator overloading being especially useful.

The lab for this module is simple, but very good for checking understanding of all the previous concepts taught in this course. It also sheds light on how some higher-level languages perform many of the basic operations which we sometimes take for granted.

Module 9

This module covers inheritance, which is a very important concept in software development as a whole. 

The first part of the module covers the broad concept of inheritance and can be very useful for those who might not have been exposed to the concepts of inheritance from other languages. The second part covers UML, which is a specific design language used for modeling software systems and includes many handy standards. It also includes an editorial about the order in which you declare class data. For further knowledge on UML, the official UML site linked on the slides or this guide can be helpful.

The section on base specifiers and the virtual base specifier is also useful when implementing objects with inheritance. 

The lab for this module is again fairly straightforward.

Module 10

This module covers polymorphism, name binding, and pure virtual functions and abstract classes.

The discussion of static vs dynamic name binding is a key detail of the C++ language, and should shed light on the use of the virtual keyword in earlier modules. 

There appears to be a typo in this module, where they say for pointer class member access operations: "For virtual functions – at time time, based on object type." I believe that this should say "runtime, based on object type."

The nuances of name binding can be very important to know for things such as keeping an array of pointers, where every pointer must be the same type. Furthermore, the concept of interfaces or abstract classes is derived from virtual name binding, as well as the pure specifier.

Please note the section on virtual destructors to prevent memory leaks.

The lab for this section is again more of an experiment, and should give you some good intuition about how many of the concepts discussed in this module work.

Module 11

This modules covers the const and constexpr specifiers and their uses and surrounding properties. 

From this module on, more and more terminology will begin to appear in the slides, especially if you're working off of the PDF rather than the regular slides. Most of it doesn't need to be memorized as much as the keywords introduced in the previous modules, as there will also be more reference guides and the like to check back to when a piece of terminology is brought up. 

The slide concerning the semantics around const member functions is worth reviewing, as the dynamics around const functions in relation to both const and non-const objects can be very useful or detrimental depending on one's understanding. Further, mutable variables and cast-to-const operations allow workarounds for these rules.

The slide reviewing the differences between the const and constexpr keywords is very useful as well.

The lab for this module is again fairly straightforward, and the exercises should give some good intuition around consts and constexprs.

Module 12

This module covers templates, both for functions and for classes, as well as their semantics.

This module has another three useful quick reference guides which can be saved for future reference. 

The concept and requires keywords are introduced for customization of the constraints around templates, which allows great flexibility and abstraction. Please note the specificity rules surrounding how a template gets chosen and the scope coexistence barrier between template and non-template.

The lab for this module is again fairly straightforward, and should allow for some practice in template creation and instantiation.

Module 13

This module covers exceptions -- a very useful concept for error handling and, as the name implies, exceptional conditions. In doing so, it covers try-catch blocks, noexcept operators, and nested exceptions. These are very important topics for "real world" code writing, and best practices in this area can benefit anyone in their coding. 

This module includes some more reference guides, as well as many good examples regarding how exceptions and exception handling is implemented in code. The references for common exceptions and exception-related functions are very good to save. Make sure to get familiar with catching and throwing and the semantics behind the two, as well as how to build your own code to gracefully use exceptions to your benefit. 

Some previous topics such a polymorphism and abstraction are brought up again in this module's context through the implementation of exception objects and nested exceptions. 

The lab for this module is fairly straightforward, and should provide some good practice in exception handling.

Module 14

This module discusses I/O streams, I/O state, formatting, and common I/O libraries.

Some of this module was covered in the first module, and it serves as a good checker for how far you've come in the course. Many of the concepts introduced in the first I/O section that may have seemed foreign should now make a lot more sense. 

Much of I/O has to do with formatting, and so rightfully this module spends a lot of time detailing the intricacies of formatting for many different aspects of I/O. It also provides more useful reference guides to help with these specifics. There are many footnotes in these lectures which provide additional knowledge on specific functions related to I/O -- these can be very good to read to fully understand what's going on in many of the slides.

The concept of delimiters and how different methods of reading and writing interact with them is very important for I/O as a whole. An additional resource can be found here.

This module covers a lot of specifics, but rather than trying to memorize it all from the slides, referencing the guides and implementing the different methods covered in the module in practice would be a much better and more organic way to learn it all should you feel the need. The common methods will naturally ingrain themselves into your memory and the uncommon methods can always be looked up when needed. This advice also generally applies to most programming concepts. 

The lab for this module is again fairly straightforward and should allow one to experience some of the intricacies discussed above firsthand.

Xcelium Simulator v22.09


Requirements

Introduction

The Xcelium simulator course introduces the Cadence Xcelium software. This software can be used to compile, elaborate, and simulate Verilog, VHDL, SystemVerilog, SystemC and other file types. To access this software you must use Clemson's Palmetto Cluster, instructions to request an account are found on the Getting Started page and instructions to access the cluster can be found above on this guide page. The Xcelium software installed on the Cluster is version 22.09, thus be sure to enroll in the 22.09 version of the course.

Information

Module 1 and Database Downloads

As always begin by downloading the required database and reading the introduction to the course. Since you will need the database file on the Palmetto Cluster Linux machine, you can either download the file from a web browser on the machine or transfer the file using the steps detailed above on this guide page. Once downloaded, the files will need to be uncompressed, steps for which are shown below.


Module 2: Introduction to Xcelium Simulation

The second module for this course gives an overview of the Xcelium Simulator, providing information such as which languages are supported, some of the different architectures and more. There are no labs for this section of the course, but be sure to take notes on the lecture.

Module 3: The xrun Utility

Module 3 introduces the most important command provided by the Xcelium software: xrun. This command can be used to compile, elaborate, and simulate HDL files. Xrun can also be run with various command-line arguments to modify its use and purpose. The lab will cover the various ways this command can be used.

Module 4: Xrun Use Models

This module covers the various ways in which the xrun command can be used to run the compilation, elaboration, and simulation processes individually. The lab once again will cover each way to do this, and is fairly straightforward.

Module 5: Incisive to Xcelium Single-Core Migration

Module 5 provides information on the Xcelium software's single core mode. There are once again no labs for this section of the course.

Module 6: The Xcelium Multi-Core Simulator

Similar to the previous module, this module provides information on the other operating mode for Xcelium: Multi-core simulation. The point of the lab for this module is to show the difference between running a simulation in single-core mode versus multi-core mode. Because of this, when running the simulation in single-core mode, it is important to be patient as the simulation may take a while (5 minutes or so). This section of the lab can be completed, however you may choose to stop at the "Simulating Design in Multi-Core Mode" section as we do not have access to the Xcelium Multi-Core Mode license and therefore cannot complete this section of the lab.

Module 7: The Xcelium and SimVision Interface

Module 7 introduces the SimVision user interface and is crucial to the simulation process. When launching SimVision on the Palmetto Cluster machines you must include the -64bit option in order for the program to work properly. This can be done in two ways, examples of each are shown below in the image carousel containing images of the Linux terminal. 


Later on in the lab, when looking for the "trace signals" side bar, look to the left side of the Register window and expand the tab by clicking the combinational logic looking symbol. Once the sidebar has been expanded click on either of the other logic-looking symbols to trace the selected signal. Look to the image above for a look at what the window looks like. 

Module 8: Executing and Analyzing a Multi-Core Example with SimVision GUI and Indago Debug Analyzer

This module will provide an example of the debug process with the Xcelium software. This module does not come with a corresponding lab.

Module 9: Race Detector

Module 9 introduces the race detector feature of the Xcelium simulator. This feature will detect any race conditions that occur in an HDL-designed system. There is one lab for this module which is fairly straightforward.

Module 10: X-Propagation

The tenth module introduces the x-propagation features of the simulator and the accompanying labs show the effects of the x-prop features. The first three labs for this module can be completed easily, however there is an issue with one of the files for the fourth lab so don't worry about any issues the simulator may give you for this section.

Module 11: X-Pessimism Solution
This module provides an example of X-pessimism and shows how the Xcelium simulator can be used to solve this issue. There are once again no labs for this section of the course.

Module 12: SystemVerilog Support and Enhancement

Module 12 covers the Xcelium features which allow for the use and operation of SystemVerilog files. There are no labs corresponding to this module.

Module 13: The Xcelium Textual Interface

This module provides information on the Xcelium "terminal" where commands can be entered to modify the simulation process. There are a couple differences between what the lab manual says and how the commands should be entered. First, when removing a stop point, be sure to enter "stop -disable stop_3". Finally, to run a simulation for a set amount of time enter "run -timepoint 50ns". This will run the simulation for 50ns.

Module 14: Debugging with SimVision and Textual/Batch Commands

This module is another "example" module which walks through an example of using the textual interface to debug a program. There are no labs for this module.

Module 15: Latest Features and Updates

As described by the title, this module simply covers the most recent features that have been added to Xcelium. Once again there are no labs for this section of the course.

Genus Synthesis Solution with Stylus Common UI v21.1

Requirements

Introduction

This course introduces Cadence's Genus Synthesis tool, which can be used to synthesize, place, and route designs. Most of this lab is done using the Genus "terminal". This tool is also used later in the Verilog Language and Application course, so it may be useful to complete this basics course before moving onto the Verilog work. Make sure to enroll in the v21.1 version of the course as this is the software edition we are licensed to use.

Information

Module 1 and Database Downloads

As always this course begins with an introduction in module 1. The final module is the database downloads page. Since Genus is a Linux-based application, the database must be downloaded and unzipped on a Linux system. The steps to do this can be found in the Xcelium Simulator course shown above on this guide page.

Module 2 - Module 4

The first 3 learning modules contain no labs and simply give an overview of the Genus application. This includes an overview of the application itself, some information on using the application, and finally an introduction to the Genus shell which will be used throughout the lab.

Module 5: Synthesis Flow in Genus

The fifth module introduces the Genus software and how to operate it by teaching some of the basic commands that are used. There are many different ways to use the set of commands with many command-line options covered throughout the course so take note of these uses. These labs require the use of a text editor, I would recommend using vim or gvim (vim with a GUI) on the Palmetto cluster, but the choice is yours (either can be launched using the vim or gvim command). The labs for module 5 require slightly more critical thinking than most courses and require you to do a lot of work on your own, however if you find yourself stuck there are solutions located in the appendices of the lab manual. During the first lab you are asked to solve an issue with the elaboration process. The manual mentions that you should see a "Done elaborating..." message, however if you are having trouble seeing this then simply run the command check_design -unresolved. This should show no errors or unresolved instances, as seen below.

Finally, labs 1-3 must be completed one after the other in one session. In other words if your Palmetto Cluster session ends, you must start again from lab 1. Lab 4 is independent of the first three, however the labs for the 6th and 7th modules also connect to labs 1-3 so it may be better to do the module 6 and 7 labs, then return to lab 5-4.

Module 6: Finding Information in the Design Hierarchy

The sixth module covers getting help while using the Genus software as well as searching for objects. As mentioned in the description of the previous module, the lab for module 6 picks up where lab 3 from module 5 ends. Therefore it is best to do the labs for modules 5 (1-3), 6, and 7 all together.

Module 7: Exploring Genus GUI

Module 7 explores the GUI that comes with the Genus software. This can be launched using the gui_show command in the Genus shell. As with lab 6, this lab must be done together with the labs from modules 5 and 6. Once the GUI is opened, look for the list showing Hier Cell - dtmf_recvr_core, x LeafCells, n Blocks on the left side. If this list in the design browser does not show this item, then right click the top item and select Top Page, as seen below. 

Later, if you encounter permission issues while trying to run the "Run" executable file, run the command chmod +x Run then simply run the file by entering ./Run Verilog and the file should execute successfully.

Modules 8-11

As with the first three modules, modules 8 through 11 do not contain any labs. The lectures for these modules cover editing a netlist, datapath synthesis, debugging and reducing runtime. These are some very important parts of the synthesis process with the Genus software so continue taking notes on these lectures.

Resources


Virtuoso Layout Design Basics vIC6.1.8

Requirements

Introduction

Cadence's Virtuoso is another EDA tool which can be used for the analysis or design of electronic circuits or PCBs. This course introduces the Virtuoso design GUI and gives a general overview of using this software. On the Palmetto Cluster, we have access to the 618 version of the software, so be sure to enroll in the vIC6.1.8 edition of the course. To launch the software on the Cluster, use the command module load cadence/IC/618 then enter virtuoso & to launch the Virtuoso software.

Information

Module 1 & Database Downloads

As with the previous two courses, this course is Linux-based, therefore you must download the lab database on a Linux machine and unzip it. Instructions for how to do this can be seen in the Xcelium Simulator course on this guide page. Module 1 simply provides and introduction to the course.

Module 2: The Design Environment

Module 2 introduces the GUI of the Virtuoso software, how to set preferences, how to use each window and what each window does. If the software prompts you for a license, click the session button until the software finds the proper license. One of the labs will require you to find the gpdk090.tf file. If you are having trouble finding the file, it is located in the custom_oa22/pdk/libs.oa22/gpdk090 file. Finally, if you need to find the float icon for the palette side bar, look to the top right of the window, as seen below.

Module 3: The User Interface

The third module covers the palette and the windows displayed within it (for example the layout or objects windows), as well as some other aspects of the GUI. When you open the GUI the layout window should already be displayed in the palette. However, if it is not, change the workspace configuration to Classic and it should appear.

The workspace configuration option is the pull down menu in the top right of the GUI, as seen in the image to the left. One of the later labs will have you use the Log Filter option, which can be found in the CIW (command window) rather than the Virtuoso Layout Suite. Finally it is important to note that any commands entered in the command window cannot contain any spaces and must always have the parentheses afterwards regardless of if there are any inputs.

Module 4: Basic and Advance Layout Commands

This module covers all sorts of commands that can be used in the Layout Suite, such as creating or editing parts. The labs for this module are fairly straightforward, however it should be noted that you should be using the custom_oa22 directory unless otherwise specified as the lab manual does not directly mention that this is the directory to be using.

Module 5: Design Rule Driven, Hierarchical Design and XStream In and Out

The final module covers some basics of viewing hierarchy and the importing and exporting translator. Once again you will need to be operating in the custom_oa22 directory for these labs. One final note, the save variant button of the create via isn't labeled (though it is the standard floppy disk symbol), but for reference the image below shows where to find it in the middle of the window.

Verilog Language and Application

Requirements

Introduction

The Cadence Verilog Language and Application course offers a basic training in using the Verilog hardware description language. This course requires the use of the Xcelium and Genus software, so completing these courses first may be beneficial. The corresponding labs require you to design some modules using Verilog, so if you find yourself seriously stuck they do have a solutions directory within the lab folder.

Information

Module 1 & Database Downloads

Module 1 gives an overview of the course while the database downloads page provides the necessary files for completing the labs for this course. For instructions on unzipping or extracting the files from the database download zip file, look to the Xcelium Simulator guide page.

Module 2: Describing Verilog Applications

The first module in this course provides an introduction regarding what Verilog is, how it can be used, and what it can be used for. The only lab corresponding to this module does not involve any work, rather it requires you to review the design you will be tasked with creating in the upcoming labs.

Module 3: Verilog Introduction

Module 3 teaches the very basics of creating a "program" or a design in Verilog. You will use this knowledge to create a multiplexer in the first lab. These labs require a lot of work to be done on your own, so as mentioned in the introduction, the course offers solutions within the database download if you find yourself stuck.

Module 4: Choosing Between Verilog Data Types

The fourth module for this course covers all sorts of topics relating to Verilog data types. This includes declaring inputs and outputs, declaring net and register variables, using vectors or arrays, etc. The lab continues with building the RISC design by having you design a Data Driver.

Module 5: Using Verilog Operators

As the title describes this module dives into using Verilog operators, either arithmetic or logical. Fittingly the lab will involve creating an ALU for the RISC design. This lab should be fairly straightforward. Refer to the resources section for a complete list of Verilog operators.

Module 6: Making Procedural Statements

Module 6 introduces procedural statements, that is the always and initial statements. These are vital to using Verilog so pay close attention with this module. The lab for this module is somewhat odd. You are tasked with making a controller or state machine of sorts. The lab manual gives you a list of outputs, the best way to do this lab is to simply "decode" the input and set the outputs accordingly. This machine is not synchronous so do not use a clock with your always statement.

Module 7: Using Blocking and Nonblocking Assignments

Module 7 covers blocking and nonblocking assignments which are special assignment operators which control the order of execution. This lab is fairly straightforward and simply requires you to create a simple register.

Module 8: Using Continuous and Procedural Assignments

In Verilog there are rules regarding which variable can be assigned values outside or inside a procedural block. This module will cover some of this information. The lab is somewhat tricky as it requires you to use a bidirectional inout type port. I've included a website which provides an example of using this port type to make this less confusing.

Module 9: Understanding the Simulation Cycle

This module covers controlling the flow of a simulation. This involves using delay statements, blocking statements, etc. The lab furthers upon this by having you create a synchronous counter which will using blocking statements within a procedural block.

Module 10: Using Functions and Tasks

As the title describes, this module introduces creating your own functions and tasks in Verilog. There is one lab for each, functions and tasks, and both are somewhat more complicated than the prior labs. Once again I have included a website which provides more information on each structure and some examples as well. These websites can be found in the resources section below. Once you get started on the function lab, you may want to delete the cnt_out output from the in-out list as the compiler does not like this option. There are other ways to assign the output than this.

Module 11: Directing the Compiler

This module covers providing instructions or inputs on the command line for the compiler to use. The lab involves using an input text file to test the functionality of the RISC you have created for the last several labs. However the names of the files and directories in the file provided in the lab directory are incorrect. Change these so the simulation can run properly, the files.txt file should look similar to the one shown below.

Module 12:  Introducing the Process of Synthesis

The twelfth module introduces synthesizing an HDL design. This lab requires the use of the cadence Genus software which can be loaded by entering module load cadence/GENUS/211. If the lab prompts you with an error regarding the GENUSHOME system variable, set this by entering export GENUSHOME=/software/commercial/cadence/GENUS211 on the linux command line to fix this.

Module 13: Coding RTL for Synthesis

Module 13 teaches the best practices for coding Verilog with Synthesis in mind. Certain practices are best and can make a design easier to synthesize. The lab for this module is quite straightforward.

Module 14: Designing Finite State Machines

This module covers an important part of a computer circuit or design: a state machine. The lab description of what your task is can be rather vague for this module so once again solutions can be found in the main directory if need be.

Module 15: Avoiding Simulation Mismatches

The fifteenth module for this course explores some root causes for errors in simulation. There are no labs for this module but these are common issues that you are likely to see while using the Verilog language so pay close attention to the lecture.

Module 16: Managing the RTL Coding Process

The sixteenth module also introduces some good coding practices such as naming nets and keeping the design organized. Once again there is not a lab associated with this module however as always the lecture teaches some very important subjects so be sure to take notes.

Module 17: Managing the Logic Synthesis Process

This module gives an overview of the logic synthesis process, what is happening, what the steps are, and how to use it. As with the past two modules there are no labs with this module.

Module 18: Coding and Synthesizing an Example Verilog Design

This module provides an example of a Verilog design and has you test a design as the lab. After testing the design in the lab you will also use a shell script to synthesize the design. This requires the use of the Genus software so once again be sure to load it before starting the lab.

Module 19: Using Verification Constructs

This module, as it describes, covers certain verification constructs such as logical equality operators, loop statements, forks, waits, etc. For the lab you are to edit the test.v file. The description of the task is somewhat vague, but it is looking for you to use a fork operation to complete the lab at hand.

Module 20: Coding Design Behavior Algorithmically

The twentieth module for this course describes different forms of modeling such as RTL, behavioral, and sequential. There are no labs associated with this module.

Module 21: Using System Tasks and System Functions

Module 21 introduces some of the pre-built tasks and functions that are included with the basic Verilog library. These are incredibly important as you will likely end up using some of these in your own work. The lab is fairly straightforward and will have you use some functions such as $display and $monitor.

Module 22: Generating Test Stimulus

This module introduces several ways to go about creating stimulus to test a design. This will lead into the next module which covers test benches. There is a lab corresponding to this module, but it should be rather straightforward.

Module 23: Developing a Testbench

Testbenches are a crucial part of the design process and are the primary tool in testing a Verilog design, so this module is very important. This module will introduce what test benches are, what they seek to do and how they go about doing it. The lab for this module requires the use of command line inputs, so when you compile the design you must include the -access +rwc options in order to enter commands while the program runs.

Module 24: Example Verilog Testbench

The final module is another example module, this time for a testbench. There are two labs corresponding to the module, both of which are fairly straightforward. The first involves using Verilog 1995 constructs, while the other uses Verilog 2001.


Resources


PCB Editor Advanced Mythologies

This is one of the most well-written labs and modules in my opinion for I was able to easily follow along with all of the steps and lectures. I highly recommend taking notes from the lectures to help out with the multiple answer questions for the exam but everything else is very easy to follow along. The only things to note is you will have to change a few settings without a step by step guide but at this point of doing the courses you should be able to navigate them without trouble otherwise please refer back to the older courses for refreshers. 

Module 3

In lab 3 you will need to load a color view file which was used in the earlier PCB courses. This image shows you where to load in the view file just in case you do not remember. 

High-Speed Constraint Management

One thing to note about this course in my experience while working was that for modules where you need to use the SigXplorer program that it would constantly quit and restart when I was using it. I tried to fully update the 17.4 version I am using in the download manager but the problem would continue. I unfortunately at the moment had to skip those parts of the lab that required the usage of the program. 

Module 2

For the Setting the Cross Section you must expand the Signal integrity section to find the impedance setting.

Module 4

For Defining Constraints for the Electrical Constraint Set you are introduce to the Differential Impedance Calculator where you are told to press the radio button next to the primary gap. I have circled what that button is referred as. 

Module 13

Remember how to update DRC's on the board. At this point for these courses, there will be multiple things that you should know how to do without too much instruction.

To pull up your status form to update DRC's select Display-Status.

Every other module you follow for this is very well structured and although you do not have the same amount of pictures as the Advanced Methodologies course, it is very straight forward to follow.

Note: I was not able to complete the modules that utilize the SigXplorer as it would keep crashing and restart when I tried to use it.

The cadence labs provides you with .brd files that will allow you to continue on to labs if you have issues without completing so this was not too big of an issue in my experience.

Allegro Update Training

This course is very straight forward and does not actually have a type of lab to follow. The purpose of this course is to explain the new features and upgrades that the PCB Editor underwent for 17.2 and 17.4. It is still an important module to learn about the features inside the program to jot down some notes for potential tools you can use in your future designs.

Allegro PCB Librarian

In this module you will learn about how to use the Project Manager 17.4 software which is just as stated in a name easy to organize a project with Cadence's many different tools. In this you will use the project manager to create and edit parts from DIPs, SOICs, and other devices. You will be able to learn about how to take footprints of the designs and edit each pin on them to be an input, CLK, OE, and whatever you need.

I personally think this is a great module that is pretty easy to follow once you already have the bases of the other courses like Entry Orcad and Basic PCB Editor from earlier. You bounce around different editors and learn a good basic for designing parts and drawings that is a good introduction for new users to the software. I believe it would be best to have this be your first module to do to get the introduction of how the cadences softwares work otherwise once you have the experience already it is very easy to follow along.