At BWRC, we want to archive "institutional knowledge" about previous test board designs so future students can peruse them and learn. Previous BWRC test board files are stored in a repo, in a group named BWRC Boards. Please contact BWRC staff to get access to that repo. We can't post the URL to that repo on this publicly-facing web site, but BWRC students and Tapeout/Bringup Students can find that information on the BWRC Resources site.
Your first step is to create a repo for your test board project. Your second step is to create 2 folders within your test board repo: one folder for your Test Plan & Board Physical Plan, and one folder for your Altium design files.
Log data about Test Board design tasks, so that future students will be able to understand the scope of a test board project. We use a shared Google Sheets doc to log data about progress of test board projects. Please fill in the data for your project as you work on it:
BWRC_Chips_and_TestBoards Data
Before you get started on a schematic, realize that you are essentially learning how to be a research manager. Our custom chips get more complicated every year. There are many steps in designing a test board. Start with thinking through what data you want to collect regarding your chip's performance. Then move on to creating a Test Plan and a Board Physical Plan. Don't dive into the mechanics of Altium until you've created those documents and pushed them to your repo.
In the discussion that follows, we're going to assume that your chip comes back from the fab already packaged, e.g. a BGA package. When you write a Test Plan, you want to think ahead about every test you'll perform during bringup. Where to start? Use this template doc to begin:
Important: Don't start schematic design for your board until you've written your Test Plan. Your Test Plan drives the design of the test board.
As you think more about the testing steps you'll need to do, you'll find that it can become quite complex. Update your Test Plan periodically and push it to your repo. We don't want information to end up orphaned in a user's personal directory. We want test board data archived where later students can understand the scope of your project.
Wishing something to be simple does not make it so.
The test board provides your chip's interface to bench-top instruments. However, the test board itself is a precision instrument, and needs to be designed to not degrade your chip's performance. For example, once your schematic is complete, you can begin layout. If you designed your schematic well, for both power and signal integrity, then good layout can be feasible - but expect to iterate. Part footprints can be tricky, so it's important to check both 2D and 3D views to make sure your board can be reliably assembled, and that you can access all test points on your board. Importantly, don't forget to spatially plan for microscope manipulators, probe station platens, wire bond interference, space for RF connector wrenches, etc. You may also need to export geometry to simulation tools to verify performance of controlled impedance traces.
Besides designing your board, you will manage other aspects of your project: design reviews with your peers to catch mistakes and learn best practices, preparing parts lists and ordering from vendors, communicating with a board house to learn their manufacturing capabilities and potentially iterating on your layout, interfacing with an assembly house to stuff your board, and even renting instruments. Staying organized is key!
Here are a few example Test Plans from previous students' test boards:
231012_TestPlan_propel-pcb_ADC_only.pptx - PROPEL-V2 chip
231212_D2D_TRX_Testing_Plan_v1.pptx - d2d-trx chip
240331_Before_Shipping_Test_Plan_hyperscale-pcb - Hyperscale chip
As you progress through your schematic design, make notes in your Board Physical Plan doc about the physical constraints you'll have in your layout. Here is an example:
231212_Board_Physical_Plan_propel-pcb.pptx - PROPEL-V2 chip