6/14/23 The Spring 2023 Tapeout Class, which just finished, taped out 3 designs (BearlyML-23, RoboChip-23 and SCuM-V23). Each was a portion of a multi-project die. Morgan State also made it into this Q2 run. Most other universities in the Intel University Design Challenge are aiming for Q3. We are the "pipe cleaner" universities. Chips might arrive back in late October 2023.
These were the specs for each design created by the Spring 23 Tapeout Class. These are not the most complete documents (ahem ...). These need to be updated and completed:
Details of anything NDA-related are left on the Tapeout Sp23 Private wiki. Another source for further details, along with design files, are posted by Intel on their Sharepoint site (which students with myfoundry2.intel.com accounts can access directly).
Here is a sub-page giving background information, primarily so that we can use common lingo. It also explains how we will use the Chipyard framework and the Terasic FPGAs to help bring up our chips:
9/1/23
The web page for this semester's class is posted on github:
https://ucb-ee290c.github.io/semesters/fa23/