Spring 2023 Tapeout

5/31/23  Note:  Due to NDA requirements, almost all the course materials and work were put on a special NDA-private wiki named Tapeout Sp23 Private Wiki.     Consequently, this page is rather bare.  We did have a session on 5/30/23 to gather feedback from the students and staff.  A number of ideas were discussed for what to do differently next Spring (Sp24).  A summary of those ideas has been posted to the page on this wiki for Fall 2023 Bringup Class.

This semester's chips will use the Intel16 process.  Throughout most of its history, Intel did not provide a foundry service for external companies, but a couple of years ago Intel did enter the foundry business.  Intel also now has a University Shuttle Program for multi-project wafers and is a major player in the new U.S. Chips Act program.  

Intel Foundry Services (IFS) - https://www.intel.com/content/www/us/en/foundry/intel-foundry-services.html

Intel University Shuttle Program news release:  https://www.hpcwire.com/2022/10/06/intel-is-opening-up-its-chip-factories-to-academia

UC Berkeley College of Engineering blog - workforce development under Chips Act

Intel is sponsoring a University Chip Design Challenge which will run later this year.  Our Spring '23 Tapeout Class will be a part of this University Challenge, albeit we will be on a run before the main Challenge gets started (to help Intel iron out the kinks for their wider contest).  My understanding is that Notre Dame and Morgan State will be with us on this foundry run which has a tapeout due date of May 5, 2023.   The rest of the universities will be shooting for the following run (tapeout due date in Aug. '23).

Our Spring 2023 Tapeout class will split up into teams to design 3 separate ASICs which will all go on the same 4mm x 4mm die.  Each team will design within a 2mm x 2mm quadrant.  Our 3 teams will get 3 of these quadrants and another university's design would be fabricated on the 4th quadrant.

Importantly, Intel will provide us not only the silicon fabrication service, but also design a ball grid array (BGA) package substrate that will be common for all universities' dies.  (A package substrate is also called an interposer, which is a fine-pitch printed circuit board).  That is, what Intel will return to us is this BGA package, consisting of our 4mm x 4mm die already attached to the top side of this interposer board, where the bottom side of the interposer board will have an array of large solder balls on a pitch that is large enough so that this BGA package can be assembled onto a printed circuit board.

Our class will split into 3 groups shown below, but there should be some commonality among all 3 ASIC teams to ensure that all 3 designs will play well with the package and have a common boot-up strategy during testing.  For instance, if all 3 ASICs pick a common set of memory boundaries and/or JTAG pinouts, then the 3 different test boards could be fairly similar, and the bootup processes would be streamlined.

So what are you allowed to put on this Tapeout/Bringup wiki?    This means that on this wiki, in the 3 teams' sub-pages linked to below, you can link to any Google Slide docs you want to create where your teammates discuss what you want to design and how you plan to architect things (i.e. how the "Digital Top" might look in Chisel), but as the design gets closer to process specifics, you need to move over to a private, restricted, wiki which we've created for students in this class (i.e. have signed the NDA).  What we're describing here is how to communicate discussions (of course, all design work with the CAD tools stays within your account on the bwrc machines).

That is, you can use these wikis to link to a Google Slide doc that you create/store on the google drive behind the respective wiki.  The idea is to use a Google Slide doc as a poor man's Slack channel, as multiple people can "Meet in the doc" to type to each other, to point to a link, to share a screenshot of interim results, etc.  Sub-teams can post a Google Slide doc whenever they have made progress 

Logistics

BWRC Computing Infrastructure slides by Brian Richards - 16 January 2023

Getting Started with Editing this Wiki - see this Tapeout/Bringup wiki's Home Page

Ed channel:  https://edstem.org/us/courses/35162

We will also have one new  lab bench (#11) in Berkeley Wireless Research Center (BWRC), in addition to the one bench (#13) which presently has the test setup for the Fall 2022 (OSCIbear21, SCuM-V22, and BearlyML22 boards, as well as Arty FPGAs and basic bench testing tools).  Here are pics of lab benches:

• 230127_BWRC_lab_bench_space

EE 194 on Berkeley Course Catalog

Course

Week 1 Lecture 1:  Intro.pptx (recording)

Lecture 2:  Chipyard.pptx (recording)

     Lab 1: Getting started with Chipyard SoC framework

Week 2 Lecture 3:  Chips.pptx (recording)

Lecture 4:  Unix & Git

  Lab 2:  VLSI Tools Flow (restricted to class private wiki, due to NDA-related material) 

Week 3 Pics of Prof. Nikolic's silicon wafers 

Week 4

Week 5

Week 6

Week 7

Week 8

Week 9.        RTL Freeze

Week 10 Spring Break

Week 11

Week 12

Week 13

Week 14

Week 14

Week 15 RRR Week

Week 16 Finals Week

Chip Testing Notes

OSCIBEAR Bringup Note

BearlyML Testing Note

SCuM-V Testing Note

Resources

Chipyard

Periperhal User Manual v0.1

EECS 151 Lectures

EECS 151 Playlist

Staff