Abstract Cadence tool for creating LEF files
ADS Analog Design System - Keysight (used to be Agilent, used to be HP) schematic, SPICE-type simulation, and 2.5D method-of-moments simulation tool
ADE Explorer Cadence Virtuoso Analog Design Environment project window for simulating schematics (uses the Cadence Spectre spice-type simulator)
Altium Designer Altium pcb tool for schematics and layout
bash Unix shell and command language
Calibre DESIGNrev Siemens Mentor - gds/oasis layout viewer, editor and design rule checker. Also called calibredrv. Calibre does both DRC & LVS.
Chipyard Open source environment of chip-design tool floow (e.g. chisel, hammer, etc.). Starts from a base conda environment.
Chisel Open source high-level chip description language (written in Scala), used in the Chipyard environment, gets compiled into verilog
conda open source, language agnostic package manager and installation tool (mostly used by the python and R communities). A modern version of pip.
csh C shell - Unix shell, command processor. Originally written in the 70s.
DVE Discovery Visual Environment - early Synopsys waveform viewer. Modern viewer now is Verdi.
emacs Editor MACroS - early text editor, written in Lisp
EMX ElectroMagnetic miXed-signal solver, by a company called Integrand which Cadence bought - finite element tool, callable from within Virtuoso
FireSim Open source FPGA-accelerated simulation tool.
Genus Cadence synthesis tool - converts elaborated verilog to gates (standard cells) that can be placed by Innovus
GIMP GNU Image Manipulation Program
git Open source distributed version control system
GTK GIMP ToolKit
GTK+ GTK re-write
GTKwave GUI TK WAVEform viewer - graphical display of .fst files (.fst files are Fast Signal Trace files)
HAMMER Highly Agile Masks Made Effortlessly from RTL - python-based tool for configuring a back-end flow, configures and calls CAD tool tcl scripts
HFSS High Frequency Simulation Software - Ansys finite element tool
HSPICE Synopsys SPICE simulator
IC virtuoso IC design environment (Cadence name up until 2015 or so)
ICADV virutoso IC ADVanced (Cadence renamed virtuoso around 2015, as these releases were for advanced nodes beyond planar CMOS)
ICADVM virtuoso IC ACVanced Methodologies (Cadence marketing folks renamed Virtuoso again around 2018)
ICC2 Synopsys IC Compiler 2 (or IC Compiler II), is a place-and-route tool similar to Cadence Innovus
ICV IC Validator - Synopsis DRC & LVS tool (IC Validator Workbench is a GUI that lets you see the layout with the DRC results, and also lets you run Vue)
Innovus Cadence automatic place and route for synthesized standard cells, similar to Synopsys ICC2
Liberate Cadence tool for creating LIB timing files
pip Pip Installs Packages - package manager for python applications and their dependencies
PLECS Piecewise Linear Electrical Circuits Simulator - Plexim's power circuits simulator
Pydantic Python library for data parsing with built-in support for json encoding/decoding
RVE Results Viewer Environment - viewer tool inside of Siemens Mentor Calibre for viewing DRCs and LVS checks
sbt Scala Build Tool - compiler for scala
Scala SCAlable LAnguage - modern high-level strongly typed programming language
Spectre Cadence simulation tool (a SPICE-type analog simulation tool, competitor to Synopsys' HSPICE)
StarRC Synopsis parasitic extraction tool (RC = resistor capacitor)
TCL Tool Command Language - early scripting language used by chip CAD industry to run tools from command line
tcsh Tenex C shell - (Tenex was an operating system). Backwards compatible with csh. Adds command-line editing and completion.
VCS Verilog Compiled Simulator - Synopsis tool (takes .v and a binary riscv executable test file (.elf file), and creates a .out file (text file of execution steps))
Verdi Synopsys debug platform, plots .fsdb (fast signal data base) files. Newer than Synopsys DVE.
Virtuoso Cadence chip layout tool
ViVA Vituoso Visualization and Analysis
Vue Synopsys IC Validator Vue tool is the interactive graphical GUI for looking at DRC results from IC Validator
Xcelium Cadence logic simulator for verification closure
Xpedition Siemens Mentor - printed circuit board schematic and layout tool (Altium calls it Expedition)
zsh Z shell