Research

Sponsors:

1. Machine Learning-related.

AI in IC Synthesis:

At leading technology nodes, the industry faces a stiff challenge to make profitable ICs. The major issues are the design rule checking (DRC) violation, timing violations, area constraint, and frequency constraints. In this research, we cohort with the DARPA IDEA program that aims for “no-human-in-the-loop” and 24-hour turnaround time to implement an IC from design specifications. To reduce human effort, we introduce new machine learning algorithms to help inexperienced engineers. Publications: DAC 2019 and MWSCAS 2019.


AI in Network Security:

The controller area network (CAN) is the most widely used intra-vehicular communication network in the automotive industry. Its simplicity in design lacks most of the requirements needed for a security-proven communication protocol. However, a safe and secure environment is imperative for autonomous as well as connected vehicles. Therefore CAN security is considered one of the essential topics in the automotive research community. In this research, we introduced novel graph-based machine learning algorithms to secure CAN bus. Publications: IEEE T-ITS 2020 and Springer JTS 2020.

AI-related Hardware: To enable real-time machine learning, we are working on an energy-efficient neuromorphic IC design.


2. Low-power, high-performance Microprocessor and SOC design applying novel clocking and signaling techniques.

Motivation:

  • Clock distribution network (CDN) consumes significant amount of dynamic power

  • This is due to the voltage-mode (VM) signaling to charge/discharge large global CDN capacitance

  • New circuit approaches for current-mode (CM) clocking save significant clock power

Current-Mode clocking:

  • The proposed CM networks are unbuffered and driven at the root by a single Tx

  • The total admittance of the network is proportional to current,

YT = β(ΣαiCox + ΣCw,j)

  • The CM clocking has huge potential to improve the power-performance of a microprocessor, system-on-chip (SOC) , FPGA-based design on future technology node

Experimental results:

  • The proposed CM scheme Saved 39-82% average power, 73% area with similar skew on industrial ISPD 2009-2010 benchmarks


3. single event upset hardened memory and soc

Motivation:

  • AEC-Q100, SEU testing required for automobile electronics with RAM > 1MB

  • SEU effect in a car microcontroller during airbag deployment could be catastrophic

seu hardening:

  • We proposed new single/double node SEU robust latch/register architecture

  • Applying novel SEU hardened circuits and system design technique could significantly improve the reliability of modern microprocessor and FPGA design

4. environmental data sensors and system

Motivation:

  • In July 12 2017, an iceberg about size of Delaware has broken off from an ice shelf on the Antarctica Peninsula