Publications
Publications
Patents
5. R. Islam, D. Challagundla, and I. Bezzam, Systems and methods of reducing wideband series resonant clock skew. US Patent Application, 18/627,479, April, 2024.
4. R. Islam, Systems and methods of graph-based vehicular intrusion detection. US Patent Application, 17713369, April, 2022.
3. M. Guthaus and R. Islam, Current-mode clock distribution. US Patent Grant, US20180076799A1, March 2018.
2. M. Guthaus and R. Islam, System and method for a hybrid current-mode and voltage-mode integrated circuit. US Patent Grant, US10691162B2, June 2020.
1. M. Guthaus and R. Islam, Current-mode clock distribution. US Patent Grant, US9787293B2, October 2017.
Journals
17. R. Islam, P. Majurski, J. Kwon, A. Sharma, and S. Krishna,, `Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks,’ MDPI (Sensors) (IF: 3.9), Volume: 24, Issue: 4, February, 2024, high downloads.
16. B. Croteau, K. Kiriakidis, T. Severson, R. Robucci, S. Rahman, and R. Islam, `State Estimation Adaptable to Cyber-Attack Using a Hardware
Programmable Bank of Kalman Filters,’ IEEE Transactions on Control Systems Technology (TCST) (IF: 4.8), Volume:, Issue:, December, 2023.
15. D. Challagundla, I. Bezzam, and R. Islam, `Design and Automation of Series Resonance Clocking in 14-nm FinFETs,’ Springer Nature Circuits, Systems and Signal Processing (CSSP) (IF: 2.3), Volume:, July 2023.
14. R. Islam, `Early-Stage DRC Prediction Using Ensemble Machine Learning Algorithms,’ IEEE CJECE (CJECE) (IF: 1.606), Volume:, Issue:, August, 2022, Acceptance rate: ~1.5%.
13. R. Islam, `Feasibility Prediction for Rapid IC Design Space Exploration,’ MDPI (Electronics) (IF: 2.69), Volume: 11, Issue: 7, July, 2022, high downloads.
12. R. Islam, R. Refat, S M Yerram, and H Malik, `Graph-Based Intrusion Detection System for Controller Area Networks,’ IEEE Transactions on Intelligent Transportation Systems (T-ITS) (IF: 9.551), Volume: 23, Issue: 3, March, 2022, high downloads.
11. R. Islam, Maloy K. Devnath, Manar D. Samad, and Syed Md Jaffrey Al Kadry, `GGNB: Graph-Based Gaussian Naive Bayes Intrusion Detection System for CAN Bus,’ Elsevier Vehicular communications (VEHCOM) (IF: 8.373), Volume: 33, November, 2021.
10. R. Islam, B. Saha, and I. Bezzam, `Resonant Energy Recycling SRAM Architecture,’ IEEE Transactions on Circuits and Systems II (TCAS-II) (IF: 3.691), Volume: 68, Issue: 4, April, 2021.
9. R. Islam and R. Refat, `Improving CAN Bus Security by Assigning Dynamic Arbitration IDs,’ Springer Nature Journal of Transportation Security (JTS) (IF: 1.46), Volume: 13, April 2020, high downloads.
8. R. Islam and M. Guthaus, `HCDN: Hybrid-Mode Clock Distribution Networks,’ IEEE Transactions on Circuits and Systems I (TCAS-I) (IF: 4.14), Volume: 66, Issue: 1, January, 2019.
7. R. Islam, `Low-Power Highly Reliable SET-Induced Dual-Node Upset Hardened Latch and Flip-Flop ,’ IEEE CJECE (CJECE) (IF: 1.606), Volume: 42, Issue: 2, January, 2019, Acceptance rate: ~1.5%.
6. R. Islam, `High-Speed On-Chip Signaling: Voltage or Current-Mode? ,’ IETE Transactions on Journal of Research (TIJR) (IF: 2.333), Volume:, Issue:, October, 2018.
5. R. Islam, `Negative Capacitance Clock Distribution ,’ IEEE Transactions on Emerging Topics in Computing (TETC) (IF: 7.691), Volume:, Issue:, September, 2018.
4. R. Islam, H. Fahmy, P. Lin and M. Guthaus, `DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis,’ IEEE Transactions on VLSI Systems (TVLSI) (IF: 2.775), Volume: 26, Issue: 10, October 2018.
3. R. Islam, `Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops,’ Springer Nature Journal of Electronic Testing: Theory and Applications (JETTA) (IF: 0.993), Volume: 34, Issue: 4, June 2018.
2. R. Islam and M. Guthaus, `CMCS: Current-Mode Clock Synthesis,’ IEEE Transactions on VLSI Systems (TVLSI) (IF: 2.775), Volume: 25, Issue: 3, March 2017, high downloads.
1. R. Islam and M. Guthaus, `Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop,’ IEEE Transactions on Circuits and Systems I (TCAS-I) (IF: 4.14), Volume: 62, Issue: 4, March 2015, high downloads.
Conferences and Presentations
19. D. Challagundla, B. Saha, I. Bezzam, and R. Islam, `A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations,’ IEEE / ACM Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Tampa Bay Area, FL, USA, June 12--12, 2024.
18. D. Challagundla, I. Bezzam, and R. Islam, `Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM),’ IEEE/ACM Design Automation Conference (DAC), WIP session, San Francisco, CA, USA, June 23-- 27, 2024.
17. D. Challagundla, B. Saha, I. Bezzam, and R. Islam, `Resonant Compute-In-Memory (RCIM) 10T SRAM Macro for Boolean Logic,’ 41st IEEE International Conference on Computer Design (ICCD), Washington DC, USA, November 2023, Acceptance rate: ~28%.
16. O. Paul, S. Abrar, R. Mu, R. Islam, and M. D. Samad, `Deep Image Segmentation for Defect Detection in Photo-lithography Fabrication,’ International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, April 5--7, 2023.
15. R. Islam, Patrick Majurski, Jun Kwon, and S. Krishna, `Exploring High-Level Neural Networks Architectures for Efficient Spiking Neural Networks Implementation,’ IEEE International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST), Dhaka, Bangladesh, January 2023, (Best Paper Award).
14. K. Kiriakidis, B. Croteau, T. Severson, E. Rodriguez-Seda, R. Robucci, R. Islam, and S. Rahman, `Degradable Tracking System based on Hardware Multi-Model Estimators,’ IEEE Resilience Week (RWS), Washington, DC, USA, September 27-29, 2022.
13. D. Challagundla, M. Galib, I. Bezzam, and R. Islam, `Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks,’ 55th IEEE International Symposium on Circuits & Systems (ISCAS) Austin, Tx, USA, May 2022.
12. R. Islam and M. A. Shahjalal, `Soft Voting-Based Ensemble Approach to Predict Early Stage DRC Violations,’ IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, Tx, USA, August 2019.
11. R. Islam and M. A. Shahjalal, `Predicting DRC Violations Using Ensemble Random Forest Algorithm,’ IEEE/ACM Design Automation Conference (DAC), Late Breaking Results (LBR) session, Las Vegas, NV, USA, June 2019.
10. R. Islam and M. Guthaus, `Low-Jitter Hybrid-Mode Clock Distribution Networks,’ IEEE/ACM Design Automation Conference (DAC), WIP session, San Francisco, CA, USA, June 2018.
9. R. Islam and M. Guthaus, `CMCS: Current-Mode Clock Synthesis,’ IEEE/ACM Design Automation Conference (DAC), WIP session, Austin, Tx, USA, June 2016.
8. R. Islam, H. Fahmy, P. Lin and M. Guthaus, `Differential Current-Mode Clock Distribution,’ IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, USA, August 25, 2015.
7. P. Lin, H. Fahmy, R. Islam and M. Guthaus, `LC Resonant Clock Resource Minimization using Compensation Capacitance,’ IEEE International Symposium on Circuits and Systems (ISCAS), Portugal, May 24-27, 2015.
6. H. Fahmy, P. Lin, R. Islam and M. Guthaus, `Switched Capacitor Quasi Adiabatic Clock,’ IEEE International Symposium on Circuits and Systems (ISCAS), Portugal, May 24-27, 2015.
5. R. Islam and M. Guthaus, `Current-Mode Clock Distribution,’ IEEE International Symposium on Circuits and Systems (ISCAS), Australia, June 1-5, 2014.
4. S. E. Esmaeili, R. Islam, A. J. Al-khalili, and G. E. R. Cowan, `Dual-Edge Triggered Sense Amplier Flip- Flop Utilizing an Improved Scheme to Reduce Area, Power, and Complexity,’ IEEE International Conference on Electronics Circuits and Systems (ICECS), Seville, Spain, December 09-12, 2012.
3. R. Islam, `A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop,’ International Symposium on Quality Electronic Design (ISQED), California, USA, March 19-21, 2012, high downloads.
2. R. Islam, S. E. Esmaeili, and T. Islam, `A High Performance Clocked Precharge SEU Hardened Flip- Flop,’ IEEE International Conference on ASIC (ASICON), Xiamen, China, October 25-28, 2011.
1. S. M. Jahinuzzaman and R. Islam, `TSPC-DICE: A Single Phase Clock High Performance SEU Hardened Flip-Flop,’ IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, USA, August 1-4, 2010, high downloads.
Thesis
Ph.D.: R. Islam, `Current-Mode Clocking and Synthesis Considering Low-Power and Skew ,' University of California Santa Cruz. Supervisor: M. Guthaus.
M.A.Sc.: R. Islam, `High-speed Energy-efficient Soft Error Tolerant Flip-flops ,' Concordia University. Supervisor: Shah. M. Jahinuzzaman. ***Here is the download statistics of my M.A.Sc. thesis until July 2020
