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Logic Synthesis
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Logic Synthesis
dc_shell> help *library*
Logic Synthesis
man attributes
help *read*
Subjects
Digital Electronics [ES 303 EC]
Unit 5
Unit 4
DSDV
DSDV LAB
DSDV Solved Previous Question Paper
TMSY Notes
Control System
Analog Electronic's
COA
Live Digital Electronics
VLSI Design
Syllabus VLSI Design
EDA Lab
Syllabus EDA Lab
CMOS_Schematics_CDL
3RD YEAR
Text Books
Computer Organization and Architecture
Syllabus
Analog Electronics [EEE]
Text Books
VLSI
Digital System Design using Verilog HDL
Professional Publications
Digital System Design with Verilog
Bikes
Engine Oil
Softwares
Certifications
MCET ECE WEBINAR
AMAZON
Trimmers
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Refrigirator
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STA
Logic Synthesis
dc_shell> help *library*
Logic Synthesis
man attributes
help *read*
Subjects
Digital Electronics [ES 303 EC]
Unit 5
Unit 4
DSDV
DSDV LAB
DSDV Solved Previous Question Paper
TMSY Notes
Control System
Analog Electronic's
COA
Live Digital Electronics
VLSI Design
Syllabus VLSI Design
EDA Lab
Syllabus EDA Lab
CMOS_Schematics_CDL
3RD YEAR
Text Books
Computer Organization and Architecture
Syllabus
Analog Electronics [EEE]
Text Books
VLSI
Digital System Design using Verilog HDL
Professional Publications
Digital System Design with Verilog
Bikes
Engine Oil
Softwares
Certifications
MCET ECE WEBINAR
AMAZON
Trimmers
Aptitude
Refrigirator
Placements
Job Openings
Colleges List
ICT Tools
Verilog
UGC NET
Lab Experiments
Analog Electronics Lab
FWR
Enquiry
Faculty Profile
TeacherOn
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PC702EC-Syllabus VLSI Design
UNIT - I
Introduction:
1.
Introduction to IC Technology
a. MOS,
b. PMOS,
c. NMOS,
d. CMOS &
e. BiCMOS Technologies
2.
Fabrication Process.
Basic Electrical Properties:
1.
Basic Electrical Properties of MOS and Bi-CMOS Circuits:
a. I
ds
-V
ds
relationships,
b. MOS transistor threshold Voltage,
c. g
m
,
d. g
ds
,
e. figure of merit;
2.
Pass transistor,
3.
NMOS Inverter,
4.
Various pull ups,
5.
CMOS Inverter analysis and design,
6.
Bi-CMOS Inverters.
UNIT - II
VLSI Circuit Design Processes:
1.
VLSI Design Flow,
2.
MOS Layers,
3.
Stick Diagrams,
4.
Design Rules and
5.
Layout, and
6.
Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates,
7.
Scaling of MOS circuits,
8.
Limitations of Scaling.
Gate Level Design:
1.
Logic Gates and Other complex gates,
2.
Switch logic,
3.
Alternate gate circuits,
4.
Basic circuit concepts,
5.
Sheet Resistance R
S
and its concept to MOS,
6.
Area Capacitance Units,
7.
Calculations – RC Delays.
UNIT - III
Subsystem Design:
1.
Shifters,
2.
Adders:
a. Carry skip,
b. carry select,
c. square root Carry Select,
d. Manchester;
3.
ALU,
4.
Multipliers:
a. Booth,
b. Baugh-Woolley,
5.
High Density Memory Elements:
a. SRAM,
b. DRAM,
c. ROM Design.
UNIT - IV
Sequential Logic Design:
1.
Behavior of Bi-stable elements,
2.
SR Latch,
3.
Clocked Latch and Flip-flop circuits,
4.
CMOS D latch and Edge triggered Flip flops.
CMOS Testing:
1.
CMOS Testing,
2.
Need for testing,
3.
Test Principles,
4.
Design Strategies for test,
5.
Chip level Test Techniques,
6.
System-level Test Techniques,
7.
Layout Design for improved Testability.
UNIT - V
Analog VLSI Design:
1.
Small signal model of MOSFETs,
2.
Simple CMOS current mirror,
3.
Common Source Amplifier,
4.
Source follower,
5.
Common Gate Amplifier,
6.
Source degenerated current mirror,
7.
Cascode Current Mirror
8.
Wilson Current Mirrors.
Suggested Readings:
1.
Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, “Essentials of VLSI circuits and systems”, PHI, 2005Edition.
2.
Weste and Eshraghian, “Principles of CMOS VLSI Design”, Pearson Education,1999.
3.
John.P. Uyemura, “Introduction to VLSI Circuits and Systems”, JohnWiley,2003.
4.
John M. Rabaey, “Digital Integrated Circuits”, PHI, EEE,1997.
5.
Wayne Wolf,” Modern VLSI Design”, Pearson Education, 3rd Edition,1997.
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