STA

[maharshi@s0 scripts]$ which pt_shell

[maharshi@s0 scripts]$ pt_shell -help

[maharshi@s0 scripts]$ pt_shell -output_log_file session_22-01-2023.log

pt_shell> set search_path /home/maharshi/verilog/verilog_codes

pt_shell> set link_path saed32rvt_tt0p78vn40c.db

pt_shell> read_verilog ripplecarryadder_4bit.v

pt_shell> current_design ripplecarryadder_4bit

pt_shell> link_design

pt_shell> current_design ripplecarryadder_4bit

pt_shell> start_gui

pt_shell> report_timing

pt_shell> report_clock

pt_shell> report_constraint

_______________________________________________________________________________________________________

//Final Script

#sta_basic_script.scr

set search_path /home/maharshi/verilog/verilog_codes

set link_path saed32rvt_tt0p78vn40c.db

read_verilog ripplecarryadder_4bit.v

current_design ripplecarryadder_4bit

link_design

current_design ripplecarryadder_4bit

start_gui

report_timing

report_clock

report_constraint

_______________________________________________________________________________________________________

Command to execute above script ==> pt_shell -file sta_basic_script.scr

1. First Step is to create a file and save it using this file name sta_basic_script.scr

2. Run this from Linux Environment but not from pt_shell

3. Make sure following lines should not be here, if yes u will get an error because those lines will get executed from [maharshi@s0 scripts]$

which pt_shell

pt_shell -help

pt_shell -output_log_file session_22-01-2023.log

_______________________________________________________________________________________________________

pt_shell> set

set set_max_delay

set_active_clocks set_max_fanout

set_activity_derate set_max_time_borrow

set_advanced_analysis set_max_transition

set_advanced_multi_input_switching_factor set_memory_percentage

set_annotated_check set_message_info

set_annotated_clock_network_power set_min_capacitance

set_annotated_delay set_min_delay

set_annotated_power set_min_library

set_annotated_transition set_min_pulse_width

set_aocvm_coefficient set_mode

set_aocvm_table_group set_multi_input_switching_analysis

set_app_var set_multi_input_switching_coefficient

set_case_analysis set_multicycle_path

set_case_sequential_propagation set_noise_derate

set_cell_mode set_noise_immunity_curve

set_clock_exclusivity set_noise_lib_pin

set_clock_gating_check set_noise_margin

set_clock_gating_percentage set_noise_parameters

set_clock_groups set_ocvm_table_group

set_clock_jitter set_operating_conditions

set_clock_latency set_opposite

set_clock_map set_output_delay

set_clock_sense set_parasitic_corner

set_clock_transition set_path_margin

set_clock_uncertainty set_pin_abstraction

set_concurrent_event_analysis_options set_port_abstraction

set_connection_class set_port_attributes

set_context_margin set_port_fanout_number

set_coupling_separation set_power_analysis_options

set_cross_voltage_domain_analysis_guardband set_power_base_clock

set_current_power_domain set_power_budget

set_current_power_net set_power_clock_scaling

set_data_check set_power_delay_shifted_event_analysis_options

set_design_attributes set_power_derate

set_design_top set_power_profile_options

set_disable_auto_mux_clock_exclusivity set_process

set_disable_check_timing set_program_options

set_disable_clock_gating_check set_propagated_clock

set_disable_pg_pins set_pulse_clock_max_transition

set_disable_timing set_pulse_clock_max_width

set_distributed_parameters set_pulse_clock_min_transition

set_domain_supply_net set_pulse_clock_min_width

set_dont_override set_qtm_attribute

set_dont_touch set_qtm_global_parameter

set_dont_touch_network set_qtm_port_drive

set_dont_use set_qtm_port_load

set_drive set_qtm_technology

set_drive_resistance set_query_rules

set_driving_cell set_rail_voltage

set_eco_options set_related_supply_net

set_eco_scenarios set_resistance

set_em_analysis_options set_retention

set_em_scaling_factor set_retention_control

set_emmp_configuration set_retention_elements

set_equal set_routing_rule

set_equivalent set_rtl_to_gate_name

set_extract_model_indexes set_rule_property

set_extract_model_margin set_rule_severity

set_false_path set_scope

set_fanout_load set_sense

set_glitch_power_analysis_options set_si_aggressor_exclusion

set_gpd_config set_si_delay_analysis

set_hier_config set_si_delay_disable_statistical

set_hier_resource_limits set_si_noise_analysis

set_host_options set_si_noise_disable_statistical

set_ideal_aggressor set_signal_em_analysis_options

set_ideal_latency set_size_only

set_ideal_network set_spacing_label_rule

set_ideal_transition set_steady_state_resistance

set_ignore_pg_function set_supply_net_probability

set_ignore_power_switches set_switching_activity

set_implement_options set_target_library_subset

set_imsa_attributes set_temperature

set_input_delay set_timing_derate

set_input_noise set_units

set_input_transition set_unix_variable

set_isolation set_user_attribute

set_isolation_control set_vector_generation_options

set_latch_loop_breaker set_voltage

set_level_shifter_strategy set_voltage_levels

set_level_shifter_threshold set_vt_mistracking_derate

set_lib_cell_spacing_label set_vt_skew_derate

set_lib_rail_connection set_waveform_integrity_analysis

set_library_driver_waveform set_wire_load_min_block_size

set_license_limit set_wire_load_mode

set_link_lib_map set_wire_load_model

set_load set_wire_load_selection_group

set_max_area setenv

set_max_capacitance

_______________________________________________________________________________________________________

pt_shell> man link_design

2. Synopsys Commands Command Reference

link_design

NAME

link_design

Resolves references in a design.

SYNTAX

string link_design

[-verbose]

[-force]

[-remove_sub_designs]

[-keep_sub_designs]

[design_name]

Data Types

design_name string

ARGUMENTS

-verbose

Displays verbose messages.

-force Forces relinking of the design. If you omit this option, the

tool does not relink a fully linked design.

-remove_sub_designs

Removes subdesigns after linking. Use this option to free up

memory and improve performance. For more information, see the

"Performance Considerations" section.

-keep_sub_designs

Keeps subdesigns after linking. By default, subdesigns are

removed. Use this option to keep the subdesigns in memory so

that the current design can be changed to other designs later.

design_name

Specifies the design to be linked; the default is the current

design.

DESCRIPTION

The link_design locates all designs and library components that are

referenced by the current design and links them to the current design.

During linking, the tool loads all files specified by the link_path

variable if they are not already in memory. Successful linking results

in a fully instantiated design on which you can perform analysis.

By default, the case sensitivity of the link is determined by the

source of the objects being linked. Although it is not recommended, you

can change the default behavior by setting the link_force_case vari-

able.

Automatic Loading of Designs and Libraries

If you set the link_path and search_path variables, you need to read

only your top-level design and then link. The tool automatically finds

and loads all other required designs and libraries.

In the following example, the newcpu.db top-level design uses the

cmos.db library. Since the link_path variable specifies cmos.db, the

link_design command loads cmos.db. As linking proceeds, the tools loads

any required design that is not already in memory by searching the

paths specified by the search_path variable. For example, the refer-

enced BOX1 design is not in memory, so the tool searches for BOX1.db in

the search_path variable and loads it.

pt_shell> set search_path "/designs/newcpu/v1.6/dbs /libs/cmos"

/designs/newcpu/v1.6/dbs /libs/cmos

pt_shell> set link_path "* cmos.db"

* cmos.db

pt_shell> read_db newcpu.db

Loading db file '/designs/newcpu/v1.6/dbs/newcpu.db'

pt_shell> link_design newcpu

Loading db file '/libs/cmos/cmos.db'

Linking design newcpu...

Loading db file '/designs/newcpu/v1.6/dbs/BOX1.db'

Loading db file '/designs/newcpu/v1.6/dbs/BOX2.db'

Loading db file '/designs/newcpu/v1.6/dbs/padring.db'

Design 'newcpu' was successfully linked.

Automatic Linking

Many PrimeTime commands attempt to link the current design for you.

For example, the report_timing command performs linking if the current

design is not linked. Automatic linking occurs only if the design is

completely unlinked, and not if the current design is partially linked

and has unresolved references. If the current design is fully linked,

there is no need for automatic linking, so it is not attempted.

You can disable automatic linking by setting the auto_link_disable

variable to true. Because determining the need for linking takes little

runtime, setting this variable is normally unnecessary. The variable

provides compatibility with Design Compiler.

Unresolved References

If the link_design command fails to resolve one or more references, you

need to correct the source of the problem and relink the design. Fail-

ures are typically caused by

o Missing libraries or designs

o Incorrectly specified link_path or search_path variable

o A file that is located in the path but not accessible by you

After making the necessary corrections, you can decide whether to do an

incremental relink or an initial link, or whether to allow the too to

create black boxes for the unresolved references.

If you can resolve the references by changing the link_path or

search_path variable, you must relink the design.

The creation of black boxes is controlled by the link_cre-

ate_black_boxes variable, which is set to true by default. Unless you

set this variable to false, the tool automatically converts each unre-

solved reference to a black box (an empty cell with no timing arcs).

The result is a completely linked design on which analysis can be per-

formed (assuming there are no other unrecoverable link errors). To

prevent unresolved references, set the link_create_black_boxes variable

to true.

Black box creation can fail when there are multiple conflicting refer-

ences, usually with generic logic. For example, if SELECT_OP has two

references, one with five pins and the other with 20 pins, the second

black box might not be created, and the design might not link. Prime-

Time does not support generic logic, except for GTECH; if a design con-

tains such generic logic, remove the design or replace it with an empty

design.

Sometimes, black box creation fails. This occurs when there are multi-

ple conflicting references. This happens most often with generic logic.

For example, if there are two references to SELECT_OP, one with five

pins, and the other with 20 pins, it is likely that the second black

box is not created and the design does not link. Other than GTECH,

PrimeTime does not support generic logic. Designs containing such

generic logic should be removed or replaced by empty designs.

Linking With Mismatches

By default, if there are pin mismatches between instance and reference,

the link_design command issues errors and fails. If you set the

link_allow_design_mismatch variable to true, the link_design command

issues warnings and continues. This allows you to gather useful infor-

mation even when part of a design is missing.

To report mismatches, use the report_design_mismatch command.

Performance Considerations

The tool starts linking with the top design along with any other loaded

designs and libraries. During the link process, other necessary designs

and libraries are loaded. When the link process completes successfully,

it produces a design that can be analyzed.

By default, all subdesigns used to build the linked design are removed

from memory. Use the -keep_sub_designs option to retain the subdesigns

if you want to

o Keep all designs and analyze them later

o Relink the design later with the -force option

Note that this option takes more memory.

You need subdesigns only if you want to analyze more than one design in

a session; the linked design contains all information necessary for

analysis. For example, in PrimeTime, wire load models are set on spe-

cific instances of the design, without requiring a subdesign.

EXAMPLES

The following examples show how a design links with many of the differ-

ent linker options. First, the link fails when a library cannot be

found in the link path because of a typo in the search path.

pt_shell> set search_path "/designs/newcpu/v1.6/dbs /libs/cmoss"

/designs/newcpu/v1.6/dbs /libs/cmoss

pt_shell> set link_path "* cmos.db"

* cmos.db

pt_shell> read_db newcpu.db

Loading db file '/design/newcpu/v1.6/dbs/newcpu.db'

pt_shell> link_design newcpu

Error: Can't read link_path file 'cmos.db' (LNK-001)

Linking design newcpu...

Loading db file '/designs/newcpu/v1.6/dbs/BOX1.db'

Loading db file '/designs/newcpu/v1.6/dbs/BOX2.db'

Loading db file '/designs/newcpu/v1.6/dbs/padring.db'

Warning: Unable to resolve reference to 'NR4' in 'newcpu'. (LNK-005)

Warning: Unable to resolve reference to 'ND2' in 'newcpu'. (LNK-005)

Warning: Unable to resolve reference to 'FD2' in 'newcpu'. (LNK-005)

Information: Design 'newcpu' was not successfully linked:

16 unresolved references. (LNK-003)

Correcting the value of the search_path variable and doing an initial

link completely links the design without black boxes.

pt_shell> set search_path "/designs/newcpu/v1.6/dbs /libs/cmos"

/designs/newcpu/v1.6/dbs /libs/cmos

pt_shell> link_design newcpu

Loading db file '/libs/cmos/cmos.db'

Linking design newcpu...

Loading db file '/designs/newcpu/v1.6/dbs/BOX1.db'

Loading db file '/designs/newcpu/v1.6/dbs/BOX2.db'

Loading db file '/designs/newcpu/v1.6/dbs/padring.db'

Design 'newcpu' was successfully linked.

SEE ALSO

current_design(2)

list_designs(2)

list_libs(2)

read_db(2)

read_ddc(2)

read_verilog(2)

read_vhdl(2)

report_design_mismatch(2)

auto_link_disable(3)

link_allow_design_mismatch(3)

link_create_black_boxes(3)

link_force_case(3)

link_path(3)

search_path(3)

Version S-2021.06-SP5

_______________________________________________________________________________________________________

pt_shell> read

read read_file read_parasitics

read_context read_fsdb read_saif

read_context_leakage_data read_hier_data read_sdc

read_db read_ivm read_sdf

read_ddc read_lib read_signal_em_rules

read_dvd read_memory_config read_vcd

read_eco_changes read_ndm read_verilog

read_eco_design read_ndm_lib read_ztdb

read_edge_annotation read_ocvm

_______________________________________________________________________________________________________

pt_shell> man read_verilog

2. Synopsys Commands Command Reference

read_verilog

NAME

read_verilog

Reads in one or more Verilog files.

SYNTAX

status read_verilog

[-hdl_compiler]

file_names

Data Types

file_names list

ARGUMENTS

-hdl_compiler

Reads the Verilog files with HDL Compiler through the PrimeTime

external reader (ptxr).

file_names

Specifies the names the files to be read.

DESCRIPTION

This command reads one or more structural, gate-level Verilog netlists

into PrimeTime. To a locate file with a relative path name, the com-

mand searches for the file in each directory specified by the

search_path variable. The command locates a file with an absolute path

name without considering the search_path variable. To determine the

file that the read_verilog command loads, use the which command.

After the Verilog files are loaded, view the design objects by using

the list_designs command. To remove designs, use the remove_design com-

mand.

The Verilog netlist must contain fully-mapped, structural designs.

PrimeTime cannot link or perform timing analysis with netlists that are

not fully mapped at the gate level. There must be no Verilog high-level

constructs in the netlist.

Reading Verilog Files With the Native Verilog Reader

By default, the read_verilog command invokes the native Verilog reader.

For large netlists, this reader is much faster and more memory-effi-

cient than HDL Compiler, but it can only read structural Verilog con-

structs. The native Verilog reader automatically reads ASCII files or

compressed gzip files. The reader uncompresses gzip files to a tempo-

rary file in the directory specified by the pt_tmp_dir variable.

Generally, the native Verilog reader does not create unconnected nets.

If you need to have these nets in your design, set the svr_keep_uncon-

nected_nets variable to true.

Structural Constructs Supported by the Native Verilog Reader

The native Verilog reader supports the following subset of the Verilog

language:

o module, endmodule

o input, output, inout

o wire

o tri, wand, wor - These constructs are supported, but they are consid-

ered to be the same as the wire construct -- that is, there is no

special significance to these constructs.

o supply0, supply1 - These constructs create wires that are logic 0 and

1, respectively.

o assign

o tran - An exception from the gate instantiation subset, tran is sup-

ported to the extent that it relates one wire to another, as with

assign. Beyond that, tran has no special significance.

If you enable the Verilog preprocessor by setting the svr_enable_vpp

variable to true, the native Verilog reader supports the following

directives:

o `define

o `else

o `endif

o `ifdef

o `include

o `undef

The PrimeTime Verilog reader reads and ignores the following constructs

o All simulation directives such as `timescale and `expand_vectornets

o parameter

o defparam

o specify, endspecify

Like HDL Compiler, the native Verilog reader accepts the translate_off

and translate_on comment directives to bypass unsupported Verilog fea-

tures.

o To turn translation off, use one of these directives:

// synopsys translate_off

/* synopsys translate_off */

o To turn translation back on, use one of these directives:

// synopsys translate_on

/* synopsys translate_on */

The following example shows how to bypass an unsupported feature:

// synopsys translate_off

nand (n2, a1, s2);

// synopsys translate_on

Assign Statements and Synonyms

The native Verilog reader creates synonyms for discarded names in an

assign statement. One net name is chosen, and the others assigned to it

are synonyms. During back-annotation, an explicitly named net can be

found through one of its synonyms. Although the get_nets command finds

nets using their synonyms, it cannot find them when mixed with any

wildcards. For example, given the assign statement of assign n1 = n2;

where n1 wins, using the get_nets command finds the real net, as in:

pt_shell> get_nets n1

{"n1"}

You can find the net using the synonym. Notice that the result is the

real net, n1, and not the synonym, n2 (which is not a real net):

pt_shell> get_nets n2

{"n1"}

You cannot use wildcards with synonyms:

pt_shell> get_nets n2*

Warning: No nets matched 'n2*' (SEL-004)

Error: Nothing matched for nets (SEL-005)

Limitations of the Native Verilog Reader

The native Verilog reader in PrimeTime does not support the following:

o Nonstructural constructs - For more information, see the "Structural

Constructs Supported by the Native Verilog Reader" section.

o Parameters - The parameter and defparam statements are read and

ignored.

o Gate instantiations

There is very limited support for global naming, that is, referencing a

wire from a different module. For example, global.gnd means wire gnd in

the global module. Global references are allowed only in instance con-

nections; they cannot be in any other context. In addition, you must

ensure the following:

o Reference is a logic constant.

o Global reference is not bussed.

o Referenced module is defined in the same file as the module that is

referencing it.

o Referenced module is defined first.

o The global name is used over the default name, but a local name is

used over the global name. For example, if global.gnd and 1'b0 are

used, gnd is the wire name; however, if ZERO is assigned to 1'b0, and

global.gnd is also used, ZERO is used.

Reading Verilog Files With HDL Compiler

Instead of using the native Verilog reader, you can optionally use the

HDL Compiler reader, which supports the complete Verilog language. How-

ever, compared to the native Verilog reader, the HDL Compiler reader

uses more CPU and memory.

To read Verilog files with HDL Compiler, use the read_verilog command

with the -hdl_compiler option. This option requires an HDL Compiler

license.

When invoking the HDL Compiler Verilog reader, the PrimeTime external

reader (ptxr) reads the .synopsys_dc.setup files (not .synopsys_pt.set-

up). These include the system, home, and local setup files. The sys-

tem setup file is always read. However, you can skip the home and local

setup files by defining the ptxr_setup_file variable in PrimeTime to

reference a user-defined ptxr-specific setup file. This user-defined

variable does not exist until you define it.

You can use the bus_naming_style variable to control bus naming, but

setting this variable in PrimeTime does not affect the reading of Ver-

ilog files with HDL Compiler.

When using the -hdl_compiler option, you can terminate the read_verilog

command by pressing Ctrl+C three times. This terminates the read

process but it does not terminate PrimeTime. This is especially useful

if you need to terminate the reading of a very long netlist file.

Limitations of Using HDL Compiler

Reading with the -hdl_compiler option has these limitations:

o Any variables that affect Verilog reading are read from .synop-

sys_dc.setup files, not from .synopsys_pt.setup. These variables can-

not be set from within PrimeTime. You can set the ptxr_setup_file

variable in PrimeTime to restrict ptxr so that it reads only the sys-

tem setup file and ignores your home and local setup files.

o Some of the error messages that appear from the read_verilog process

cannot be found using the man command from PrimeTime. You can access

these message man pages from other Synopsys shells or from the UNIX

man command.

o Pragmas are ignored.

o No warnings are issued if unmapped logic or HDL constructs exist in

the Verilog netlist.

EXAMPLES

In the following example, the file newcpu.v is read based on the

search_path.

pt_shell> set search_path "/designs/newcpu/v1.6 /libs/cmos"

/designs/newcpu/v1.6 /libs/cmos

pt_shell> read_verilog newcpu.v

Loading verilog file '/designs/newcpu/v1.6/newcpu.v'

pt_shell> remove_design -all

Removing design newcpu...

pt_shell> read_verilog newcpu.v -hdl_compiler

Beginning read_verilog...

Loading db file '/release/libraries/syn/standard.sldb'

Loading db file '/release/libraries/syn/gtech.db'

Loading verilog file '/designs/newcpu/v1.6/newcpu.v'

Reading in the Synopsys verilog primitives.

/designs/newcpu/v1.6/newcpu.v:

SEE ALSO

list_designs(2)

remove_design(2)

which(2)

bus_naming_style(3)

pt_tmp_dir(3)

ptxr_setup_file(3)

search_path(3)

svr_enable_vpp(3)

svr_keep_unconnected_nets(3)

Version S-2021.06-SP5

_______________________________________________________________________________________________________

pt_shell> man current_design

2. Synopsys Commands Command Reference

current_design

NAME

current_design

Sets or returns the current design.

SYNTAX

string current_design

[design_name]

Data Types

design_name string

ARGUMENTS

design_name

Specifies the working or focal design for many PrimeTime com-

mands. If you omit the design_name option, the current_design

command returns a collection containing the current design. If

the design_name option specifies a design that cannot be found,

an error is issued and the working design remains unchanged.

DESCRIPTION

This command sets or returns the working design, which is the focus of

many PrimeTime commands. Before link_design current_design won't

return anything. Without arguments, the current_design command returns

a collection containing the current working design. Together, the cur-

rent_design and current_instance commands define the focus for many

PrimeTime commands.

To display designs currently available in PrimeTime, use the

list_designs command.

EXAMPLES

The following example uses the current_design command to show the cur-

rent context and to change the context from one design to another.

pt_shell> current_design

{"TOP"}

pt_shell> list_designs

Design Registry:

ADDER /designs/dbs/my_design.db:ADDER

FULL_ADDER /designs/dbs/my_design.db:FULL_ADDER

FULL_SUBTRACTOR /designs/dbs/my_design.db:FULL_SUBTRACTOR

HALF_ADDER /designs/dbs/my_design.db:HALF_ADDER

HALF_SUBTRACTOR /designs/dbs/my_design.db:HALF_SUBTRACTOR

SUBTRACTOR /designs/dbs/my_design.db:SUBTRACTOR

* TOP /designs/dbs/my_design.db:TOP

pt_shell> current_design ADDER

{"ADDER"}

pt_shell> current_design

{"ADDER"}

The current_design command can be used as a parameter to other pt_shell

commands. In the following example, the remove_design command is used

to delete the working design from pt_shell.

pt_shell> current_design

{"TOP"}

pt_shell> remove_design [current_design]

Removing design 'TOP'...

pt_shell> current_design

Error: Current design is not defined. (DES-001)

pt_shell>

SEE ALSO

current_instance(2)

list_designs(2)

Version S-2021.06-SP5

_______________________________________________________________________________________________________

pt_shell> set link

link_allow_design_mismatch link_keep_unconnected_cells

link_create_black_boxes link_library

link_force_case link_path

link_keep_cells_with_pg_only_connection link_path_per_instance

link_keep_pg_connectivity

_______________________________________________________________________________________________________

pt_shell> man link_allow_design_mismatch

3. Attributes and Variables Command Reference

link_allow_design_mismatch

NAME

link_allow_design_mismatch

Controls the behavior of the link design when pin mismatch

between instance and reference occur.

TYPE

Boolean

DEFAULT

false

DESCRIPTION

This variable controls whether design linking succeeds when pin mis-

matches between instance and reference occur. By default, linking fails

if there are pin mismatches between the instance and reference. For

example, when a pin exists in the instance but does not exist in the

library, link issues an error and fails.

If you set this variable to true, the extra pin is ignored, and design

linking continues. This allows you to gather useful information even if

part of a design is missing.

Common causes of mismatches include:

1. A pin has different directions in instance and reference.

2. A pin of instance does not exist in reference.

3. A bus has different widths in instance and reference.

When a mismatch occurs, the reference always take precedence.

o In case 1, the direction of the pin in the linked design is from the

reference.

o In case 2, the pin is ignored and does not exist in the reference.

o In case 3, all extra bits in the instance are ignored, and the bus

width in the linked design is the same as the bus width from the ref-

erence.

Note that for bus width mismatches, the least significant bit of

instance is mapped to least significant bit of the reference; all extra

bits of the instance are ignored, and all extra bits of the reference

are dangling.

To report mismatches found during link, use the report_design_mismatch

command.

SEE ALSO

link_design(2)

report_design_mismatch(2)

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pt_shell> man link_keep_unconnected_cells

3. Attributes and Variables Command Reference

link_keep_unconnected_cells

NAME

link_keep_unconnected_cells

Keeps unconnected cells after design linking.

TYPE

Boolean

DEFAULT

false

DESCRIPTION

This variable controls whether to keep unconnected cells after design

linking.

o false (the default) - Discards unconnected cells. By default, the

tool also discards cells that are connected to only power/ground (PG)

nets; to keep cells that are connected to only PG nets, set the

link_keep_cells_with_pg_only_connection to true.

o true - Keeps unconnected cells. With this setting, the tool also

keeps cells that are connected to PG nets, regardless of the

link_keep_cells_with_pg_only_connection variable setting.

You must set this variable before you load designs and libraries into

PrimeTime.

SEE ALSO

link_design(2)

link_keep_cells_with_pg_only_connection(3)

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pt_shell> man link_create_black_boxes

3. Attributes and Variables Command Reference

link_create_black_boxes

NAME

link_create_black_boxes

Enables design linking to automatically convert unresolved ref-

erences into black boxes.

TYPE

Boolean

DEFAULT

true

DESCRIPTION

By default, this variable is set to true, and design linking automati-

cally converts each unresolved reference into a black box, an empty

cell with no timing arcs. The result is a completely linked design on

which you can analysis.

If you set this variable to false, unresolved references remain unre-

solved, and most analysis commands cannot work.

SEE ALSO

link_design(2)

search_path(3)

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pt_shell> man link_path

3. Attributes and Variables Command Reference

link_path

NAME

link_path

Specifies a list of libraries, design files, and library files

used during linking.

TYPE

list

DEFAULT

DESCRIPTION

This variable specifies a list of libraries, design files, and library

files used during linking. The link_design command looks at those files

and tries to resolve references in the order that you specify.

The link_path variable can contain three types of elements: *, a

library name, or a file name.

The "*" entry in the value of this variable indicates that the

link_design command should search all the designs loaded in the

pt_shell while trying to resolve references. Designs are searched in

the order in which they were read.

For elements other than "*", PrimeTime searches for a library that has

already been loaded. If that search fails, PrimeTime searches for a

file name using the search_path variable.

The libraries that are specified by the link_path variable are loaded

in parallel with Verilog files during the read_verilog command. For

best runtime performance, set the search_path and link_path variables

before you run the read_verilog command.

SEE ALSO

link_design(2)

link_path_per_instance(3)

search_path(3)

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pt_shell> man link_library

3. Attributes and Variables Command Reference

link_library

NAME

link_library

This is a synonym for the link_path variable.

SEE ALSO

link_path (3)

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pt_shell> man link_force_case

3. Attributes and Variables Command Reference

link_force_case

NAME

link_force_case

Controls the case sensitivity behavior of the link design com-

mand.

TYPE

string

DEFAULT

check_reference

DESCRIPTION

This variable controls the case-sensitive or insensitive behavior of

the link_design command. Allowed values are the default of check_refer-

ence, case_sensitive, or case_insensitive. The check_reference option

means that the case sensitivity of the link is determined only by the

case sensitivity of the input format that created that reference. For

example, a VHDL reference is linked case-insensitively, whereas a Ver-

ilog reference is linked case-sensitively.

Some caveats apply to this variable, as follows:

1. Do not set the link_force_case variable to case_insensitive if you

are reading in source files from case-sensitive formats (for example,

Verilog). Doing so could cause inconsistent, unexpected, and undesir-

able results. For example, you might have an instance u1 of design

'inter', but might have loaded a design 'Inter'. If you do a case-

insensitive link, you get design 'Inter'. The side effect is that the

relationship between u1 and 'inter' is gone; it has been replaced by a

relationship between u1 and 'Inter'. Changing the link_force_case vari-

able back to check_reference or case_sensitive does not restore the

original relationship. You would have to remove the top design, reload

it, and relink. Note: Design Compiler has the same restriction.

2. Do not change the value of this variable within a session. Doing so

could cause numerous error and warning messages that can cause confu-

sion.

3. Setting the link_force_case variable to case_insensitive can

decrease the performance of the link_design command.

SEE ALSO

link_design(2)

link_create_black_boxes(3)

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pt_shell> man link_path

3. Attributes and Variables Command Reference

link_path

NAME

link_path

Specifies a list of libraries, design files, and library files

used during linking.

TYPE

list

DEFAULT

DESCRIPTION

This variable specifies a list of libraries, design files, and library

files used during linking. The link_design command looks at those files

and tries to resolve references in the order that you specify.

The link_path variable can contain three types of elements: *, a

library name, or a file name.

The "*" entry in the value of this variable indicates that the

link_design command should search all the designs loaded in the

pt_shell while trying to resolve references. Designs are searched in

the order in which they were read.

For elements other than "*", PrimeTime searches for a library that has

already been loaded. If that search fails, PrimeTime searches for a

file name using the search_path variable.

The libraries that are specified by the link_path variable are loaded

in parallel with Verilog files during the read_verilog command. For

best runtime performance, set the search_path and link_path variables

before you run the read_verilog command.

SEE ALSO

link_design(2)

link_path_per_instance(3)

search_path(3)

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pt_shell> man link_keep_cells_with_pg_only_connection

3. Attributes and Variables Command Reference

link_keep_cells_with_pg_only_connection

NAME

link_keep_cells_with_pg_only_connection

Keeps cells that are connected to only power or ground (PG) nets

after design linking.

TYPE

Boolean

DEFAULT

false

DESCRIPTION

This variable controls whether to keep cells that are connected only to

power or ground (PG) nets after design linking. This variable is

ignored if the link_keep_unconnected_cells variable is set to true.

o false (the default) - Deletes cells that are connected only to PG

nets.

o true - Keeps cells that are connected only to PG nets.

You must set this variable before you load designs and libraries into

PrimeTime.

SEE ALSO

link_design(2)

link_keep_unconnected_cells(3)

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pt_shell> man link_path_per_instance

3. Attributes and Variables Command Reference

link_path_per_instance

NAME

link_path_per_instance

Overrides the default link path for selected leaf cell or hier-

archical cell instances.

TYPE

list

DEFAULT

(empty)

DESCRIPTION

This variable, which takes effect only if set before linking the cur-

rent design, overrides the default link_path variable for selected leaf

cell or hierarchical cell instances. The format is a list of lists.

Each sublist consists of a pair of elements: a set of instances, and a

link_path specification that should be used for and within these

instances. For example,

set link_path {* lib1.db}

set link_path_per_instance [list

[list {ucore} {* lib2.db}]

[list {ucore/usubblk} {* lib3.db}]]

Entries are used to link the specified level and below. If a given

block matches multiple entries in the per-instance list, the more spe-

cific entry overrides the more general entry. In the preceding example:

1. lib3.db would be used to link blocks 'ucore/usubblk' and below.

2. lib2.db would be used to link 'ucore' and below (except within

'ucore/subblk').

3. lib1.db would be used for the remainder of the design (everything

except within 'ucore').

The default value of the link_path_per_instance variable is an empty

list, meaning that the feature is disabled.

SEE ALSO

link_design(2)

link_path(3)

link_path_per_instance(3)

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pt_shell> man link_keep_pg_connectivity

3. Attributes and Variables Command Reference

link_keep_pg_connectivity

NAME

link_keep_pg_connectivity

Enables the Verilog PG flow, which reads in Verilog PG netlist

and derives the rail connectivity data from that netlist.

TYPE

Boolean

DEFAULT

false

DESCRIPTION

By default, the PrimeTime tool uses UPF-specified power intent and

ignores PG connectivity information in Verilog netlists. However, you

can optionally have the tool to derive PG connectivity from a PG Ver-

ilog netlist, in which case there is no need to load UPF files.

To do this, set the link_keep_pg_connectivity variable to true before

you read in any design information. When you read in the netlist, the

tool derives the UPF power intent from the PG netlist data and implic-

itly updates the design database as if it were running UPF commands

like create_power_domain, create_supply_port, create_supply_net, and

connect_supply_net. After you link the design, you can set the supply

voltages by using the set_voltage command, just like the UPF flow.

This PG netlist flow works with design data generated in either the

UPF-prime flow or the golden UPF flow. It supports PrimeTime features

such as timing analysis, voltage scaling, power switches, and ECOs.

Note that the PG netlist flow requires all the netlists to have PG

information; it does not accept mixture of PG and non-PG netlists.

Loading the UPF file might be necessary for using the extract_model

command in combination with the set_port_attributes and

set_related_supply_net commands.

To enable reconnection of supply nets to PG pins that already have con-

nections in the PG connectivity from the netlist, set the

pg_allow_pg_pin_reconnection variable to true.

SEE ALSO

connect_supply_net(2)

create_power_domain(2)

create_power_switch(2)

create_supply_port(2)

pg_allow_pg_pin_reconnection(3)

Version S-2021.06-SP5

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