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PC653EC

DIGITAL SYSTEM DESIGN THROUGH VERILOG HDL LAB

Course Objectives:

1. Describe Verilog HDL and develop digital circuits using gate level and data flow modeling

2. Develop Verilog HDL code for digital circuits using switch level and behavioral modeling

3. Design and develop of digital circuits using Finite State Machines (FSM)

4. Perform functional verification of above designs using Test Benches.

5. Implementation of experiments on FPGA/CPLD boards.

Course Outcomes: The students able to

1. Appreciate the constructs and conventions of the Verilog HDL programming in gate level and data flow modeling.

2. Generalize combinational circuits in behavioral modeling and concepts of switch level modeling

3. Design and analyze digital systems and finite state machines.

4. Perform functional verification by writing appropriate test benches.

5. Implement designs on FPGA/CPLD boards.

List of Experiments

Write the Code using VERILOG, Simulate and synthesize the following:

1. Write structural and dataflow Verilog HDL models for

a) 4-bit ripple carry adder.

b) 4-bit carry Adder – cum Subtractor.

c) 2-digit BCD adder / subtractor.

d) 4-bit carry look ahead adder

e) 4-bit comparator - Logic Diagram

2. Write a Verilog HDL program in Hierarchical structural model for

a) 16:1 mux realization using 4:1 mux

b) 3:8 decoder realization through 2:4 decoder

c) 8-bit comparator using 4-bit comparators and additional logic - Logic Diagram

3. Write a Verilog HDL program in behavioral model for

a) 8:1 mux

b) 3:8 decoder

c) 8:3 encoder

d) 8-bit parity generator and checker

4. Write a Verilog HDL program in structural and behavioral models for

a) 8 bit asynchronous up-down counter

b) 8 bit synchronous up-down counter

5.a Write a Verilog HDL program for 4-bit sequence detector through Meal State Machine

5.b Write a Verilog HDL Program for 4-bit Sequence Detector through Moore state machines.

6. Write a Verilog HDL program for traffic light controller realization through state machine.

7. Write a Verilog HDL program for vending machine controller through state machine. - GitHub

8. Write a Verilog HDL program in behavioral model for 8-bit shift and add multiplier.

9. Write a Verilog HDL program in structural model for 8-bit Universal Shift Register. - GitHub

For 4-bit Universal Shift Register - PPT

2'b00 = No Change

2'b01 = Shift Right

2'b10 = Shift Left

2'b11 = Parallel Load

10. Write a Verilog HDL program for implementation of data path and controller units

a) Serial Adder - Word Doc - PDF WORKING

b) ALU

Note:

1. All the programs should be simulated using test benches.

2. Minimum of two experiments to be implemented on FPGA/CPLD boards.

Mandatory Softwares:

1. Internet Download Manager

2. Any Desk

3. Adobe Acrobat

4. Office 365

5. Xilinx ISE 14.7

1. moore_0100_sequence

1. Verilog Code for Basic Gates

   1. AND Gate

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   2. OR Gate

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   3. NOT GATE

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

2. Verilog Code for Universal Gates

   1. NAND Gate

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   2. NOR Gate

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

3. Verilog Code for Exclusive Gates

   1. XOR Gate

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   2. XNOR Gate

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

4. Verilog codes for Combinational Circuits

   1. Half Adder

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   2. Full Adder

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   3. Half Subtractor

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   4. Full Subtractor

      1. Gate Level Modelling

      2. Data Flow Modelling

      3. Behavioural Modelling

   5. Multiplexer

      1. 2:1

         1. Gate Level Modelling

         2. Data Flow Modelling

         3. Behavioural Modelling

      2. 4:1

         1. Gate Level Modelling

         2. Data Flow Modelling

         3. Behavioural Modelling

      3. 8:1

         1. Gate Level Modelling

         2. Data Flow Modelling

         3. Behavioural Modelling

   6. Demultiplexer

      1. 1:2

         1. Gate Level Modelling

         2. Data Flow Modelling

         3. Behavioural Modelling

      2. 1:4

         1. Gate Level Modelling

         2. Data Flow Modelling

         3. Behavioural Modelling

      3. 1:8

         1. Gate Level Modelling

         2. Data Flow Modelling

         3. Behavioural Modelling

   7. Encoder

   8. Priority Encoder

   9. Decoder

   10. Comparator

   11. Write structural and dataflow Verilog HDL models for

       1. 4-bit Ripple Carry Adder

       2. 4-bit Ripple Carry Adder cum Subtractor

       3. 2-digit BCD Adder / Subtractor

       4. 4- bit Carry Look aHead Adder

       5. 4-bit Comparator

   12. Write a Verilog HDL program in Hierarchical structural model for

       1. 16:1 mux realization using 4:1 mux

       2. 3:8 decoder realization through 2:4 decoder

       3. 8-bit comparator using 4-bit comparators and additional logic

   13. Write a Verilog HDL program in behavioral model for

       1. 8:1 mux

       2. 3:8 decoder

       3. 8:3 encoder

       4. 8-bit parity generator and checker

   14. Write a Verilog HDL program in structural and behavioral models for

       1. 8 bit asynchronous up-down counter

       2. 8 bit synchronous up-down counter

   15. Write a Verilog HDL program for 4-bit sequence detector through Mealy and Moore state machines

   16. Write a Verilog HDL program for traffic light controller realization through state machine

   17. Write a Verilog HDL program for vending machine controller through state machine

   18. Write a Verilog HDL program in behavioral model for 8-bit shift and add multiplier

   19. Write a Verilog HDL program in structural model for 8-bit Universal Shift Register

   20. Write a Verilog HDL program for implementation of data path and controller units

       1. Serial Adder

       2. ALU

Viva Questions

1. Abbreviate DSDV

2. Abbreviate HDL

3. Abbreviate ISE

4. What is meant by Synthesis

5. What is Simulation

6. What is the use of source code

7. What is the use of Test Bench

8. What is Register

9. Types of Registers

10. Logic Gates working with Truth Tables and K-Maps

11. What is Comparator

12. Boolean Expressions of Comparator

13. Difference between Binary Addtion and BCD Addition Explain with Example

14. What is the use of #

15. What is the use of $

16. Different types of Operators

17. Styles of Modelling

18. How Switch Level Modelling is different compared to other styles of modelling

19. What are Compiler Directives

20. Difference between Synchronous and ASynchronous

21. What is the difference between Encoding and Encoder

22. What is the difference between Decoding and Decoder

23. Difference between Parity Generator and Parity Checker

24. Difference between Half Adder and Full Adder

25. There exist Ha,FA What is the need of RCA

26. How CLA is different from RCA

27. In BCD Addition why you are adding only +6 for correction

28. What is meant by Adder cum Subtractor explain its working

29. Difference between Scalar and Vector

30. Difference between Task and Function

31. Difference between Parallel Adder and Serial Adder

32. Difference between FSM and ASM