dc_shell> man attributes
3. Attributes and Variables Command Reference
attributes
NAME
attributes
Lists the predefined Synopsys attributes.
DESCRIPTION
Attributes are properties assigned to objects such as nets, cells, and
clocks, and describe design features to be considered during optimiza-
tion.
Attributes are grouped into the following categories:
o cell
o clock
o design
o library cell
o net
o pin
o port
o read-only
o reference
Definitions for these attributes are provided in the subsections that
follow.
There are several commands used to set attributes; however, most
attributes can be set with the set_attribute command. If the attribute
definition specifies a set command, use it to set the attribute. Oth-
erwise, use the set_attribute command.
Some attributes are informational, or read-only. You cannot set the
value of these attributes. Most attribute groups contain read-only
attributes; however, a complete list of these attributes is provided in
the "Read Only" subsection.
Some attributes are instance-specific, which means they can be applied
to specified objects in the design hierarchy. The following attributes
are instance-specific:
o disable_timing
o load
o test_assume
Certain attributes are specific to Power Compiler objects. For infor-
mation about the Power Compiler attributes, see the power_attributes
man page.
To determine the value of an attribute, use the get_attribute command.
To remove attributes, use the remove_attribute command.
For a more detailed explanation of the attributes, see the man pages of
the appropriate set command.
Note that path groups, cell delay, net delay, external delay, point-to-
point timing specification, and arrival information are not represented
as attributes, and therefore cannot be manipulated with attribute com-
mands.
Cell Attributes
async_set_reset_q
Establishes the value (0 or 1) that should be assigned to the q
output of an inferred register if set and reset are both active
at the same time. To be used with the async_set_reset_qn
attribute. Use these attributes if one of the following condi-
tion sets apply:
o You have used the one_hot or one_cold attribute or directive
in your HDL description and your logic library is written
using pre-V3.0a syntax
o Your logic library does not use a consistent convention for q
and qn when set and reset are both active
By default, if set and reset are both active at the same time,
Design Compiler uses the convention of the selected logic
library, as set with the target_library variable. Set this
attribute with the set_attribute command.
async_set_reset_qn
Establishes the value (0 or 1) that should be assigned to the qn
output of an inferred register if set and reset are both active
at the same time. To be used with the async_set_reset_q
attribute. Use these attributes if one of the following condi-
tion sets apply:
o You have used the one_hot or one_cold attribute or directive
in your HDL description and your logic library is written
using pre-V3.0a syntax
o Your logic library does not use a consistent convention for
q and qn when set and reset are both active
If a V3.0a or later syntax logic library is used, then by
default, if set and reset are both active at the same time,
Design Compiler will use the convention of the selected logic
library (target_library). Set with set_attribute.
If you are unsure whether or not your logic library uses V3.0a
syntax, ask your ASIC vendor.
combinational_type_exact
Specifies the replacement gate to use for cells specified in the
cell list. Compile attempts to convert combinational gates
tagged with set_compile_type to the specified replacement combi-
national gate. Set with set_combinational_type.
disable_timing
Disables the timing arcs of a cell. This has the same effect on
timing as not having the arc in the library. Set with set_dis-
able_timing.
dont_touch
Identifies cells to be excluded from optimization. Values are
true (the default) or false. Cells with the dont_touch
attribute set to true are not modified or replaced during com-
pile. Setting dont_touch on a hierarchical cell sets the
attribute on all cells below the hierarchical cell. Set with
the set_dont_touch command.
flip_flop_type
Stores the name of the specified flip-flop to be converted from
the target_library. The compile command automatically converts
all tagged flip-flops to the specified (or one similar) type.
Set with set_register_type -flip_flop flip_flop_name [cell_list]
.
flip_flop_type_exact
Stores the name of the specified flip-flop to be converted from
the target_library. The compile command automatically converts
all tagged flip-flops to the exact flip-flop type. Set with
set_register_type -exact -flip_flop flip_flop_name [cell_list] .
is_black_box
Sets to true if the cell's reference is not linked to a design
or is linked to a design that does not have a functionality.
This attribute is read-only and cannot be set by the user.
is_combinational
Sets to true if all cells of a design and all designs in its
hierarchy are combinational. A cell is combinational if it is
non-sequential or non-tristate and all of its outputs compute a
combinational logic function. The report_lib command reports
such a cell as not a black-box.
This attribute is read-only and cannot be set by the user.
is_dw_subblock
Sets to true if the object (a cell, a reference, or a design) is
a DW subblock that was automatically elaborated.
This attribute is read-only and cannot be set by the user.
Note that DW subblocks that are manually elaborated do not have
this attribute.
is_hierarchical
Sets to true if the design is not a leaf design; for example,
not from a logic library.
This attribute is read-only and cannot be set by the user.
is_mapped
Sets to true if the cell is not generic logic.
This attribute is read-only and cannot be set by the user.
is_sequential
Sets to true if the cell is sequential. A cell is sequential if
it is not combinational.
This attribute is read-only and cannot be set by the user.
is_synlib_module
Sets to true if the object (a cell, a reference, or a design)
refers to an unmapped module reference, or if the object is (or
refers to) a design that was automatically elaborated from a
synlib module or a synlib operator.
This attribute is read-only and cannot be set by the user.
Note that synlib modules that are manually elaborated do not
have this attribute.
is_synlib_operator
Sets to true if the object (a cell or a reference) is a syn-
thetic library operator reference.
This attribute is read-only and cannot be set by the user.
is_test_circuitry
Sets by insert_dft on the scan cells and nets added to a design
during the addition of test circuitry.
This attribute is read-only and cannot be set by the user.
is_unmapped
Sets to true if the cell is generic logic.
This attribute is read-only and cannot be set by the user.
latch_type_exact
Stores the name of the specified latch to be converted from the
target_library. The compile command automatically converts all
tagged latches to the exact latch type. Set with set_regis-
ter_type -latch latch_name [cell_list] .
map_only
Specifies that compile attempts to map the object exactly in the
target library, and exclude the object from logic-level opti-
mization (flattening and structuring) when set to true. The
default is false. Set with set_map_only.
max_fall_delay
Specifies a floating-point value that establishes the maximum
falling delay on ports, clocks, pins, cells, or on paths between
such objects. Set with set_max_delay.
max_rise_delay
Specifies a floating-point value that establishes the maximum
rising delay on ports, clocks, pins, cells, or on paths between
such objects. Set with set_max_delay.
max_time_borrow
Specifies a floating-point number that establishes an upper
limit for time borrowing; that is, it prevents the use of the
entire pulse width for level-sensitive latches. Units are those
used in the logic library. Set with set_max_time_borrow.
min_fall_delay
Specifies a floating-point value that establishes the minimum
falling delay on ports, clocks, pins, cells, or on paths between
such objects. Set with set_min_delay.
min_rise_delay
Specifies a floating-point value that establishes the minimum
rising delay on ports, clocks, pins, cells, or on paths between
such objects. Set with set_min_delay.
ref_name
Specifies the reference name of a cell.
This attribute is read-only and cannot be set by the user.
full_name
Specifies the hierarchical name of cell, pin or net.
This attribute is read-only and cannot be set by the user.
scan Specifies that the cell is always replaced by an equivalent scan
cell during insert_dft when set to true. When set to false, the
cell is not replaced. Set with set_scan.
scan_chain
Includes the specified cells of the referenced design in the
scan-chain whose index is the value of this attribute. Set with
set_scan_chain.
scan_element
Determines if sequential cells in the specified designs are
replaced by equivalent scan cells during insert_scan. When
true, the default, insert_scan replaces cell_design_ref_list
with equivalent scan cells. The scan cells are not replaced
when set to false. Set with set_scan_element.
scan_latch_transparent
Makes specified cells transparent during ATPG when set to true.
For hierarchical cells, the effects apply hierarchically to
level-sensitive leave cells. Set with set_scan_transparent.
Remove with remove_attribute.
test_isolate
Indicates that the specified sequential cells, pins, or ports
are to be logically isolated and considered untestable during
test design rule checking by check_test. When this attribute is
set on a cell, it is also placed on all pins of that cell. Do
not set this attribute on a hierarchical cell. Use report_test
-assertions for a report on isolated objects. Set with
set_test_isolate.
Note that setting this attribute suppresses the warning messages
associated with the isolated objects.
test_routing_position
Specifies the preferred routing order of the scan-test signals
of the identified cells. Set with set_test_routing_order.
ungroup
Removes a level of hierarchy by exploding the contents of the
specified cell in the current design. If specified on a refer-
ence object, cells using that reference are ungrouped during
compile. Set with set_ungroup.
register_list
Specifies the single-bit cells that are remapped to the multibit
cell. This attribute can be set when the compile_ultra or the
create_regsiter_bank commands remap single-bit registers to
multibit registers.
Clock Attributes
clock_fall_transition
Sets the falling transition value on the specified clock list.
The clock_fall_transition overrides the calculated transition
times on clock pins of registers and associated nets. Set using
set_clock_transition.
clock_rise_transition
Sets the rising transition value on the specified clock list.
The clock_rise_transition overrides the calculated transition
times on clock pins of registers and associated nets. Set using
set_clock_transition.
dont_touch_network
When a design is optimized, compile assigns dont_touch
attributes to all cells and nets in the transitive fanout of
dont_touch_network ports. The dont_touch assignment stops at
the boundary of storage elements. An element is recognized as
storage only if it has setup or hold constraints. Set with
set_dont_touch_network.
fix_hold
Specifies that compile should attempt to fix hold violations for
timing endpoints related to this clock. Set with set_fix_hold.
hold_uncertainty
Specifies a negative uncertainty from the edges of the ideal
clock waveform. Set with set_clock_uncertainty -hold.
max_fall_delay
A floating point value that specifies the maximum falling delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_max_delay.
max_rise_delay
A floating point value that specifies the maximum rising delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_max_delay.
max_time_borrow
A floating point number that establishes an upper limit for time
borrowing; that is, it prevents the use of the entire pulse
width for level-sensitive latches. Units are those used in the
logic library. Set with set_max_time_borrow.
min_fall_delay
A floating point value that specifies the minimum falling delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_min_delay.
min_rise_delay
A floating point value that specifies the minimum rising delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_min_delay.
period Assigns a value to the clock period. The clock period (or cycle
time) is the shortest time during which the clock waveform
repeats. For a simple waveform with one rising and one falling
edge, the period is the difference between successive rising
edges. Set with create_clock -period_value.
propagated_clock
Specifies that the clock edge times be delayed by propagating
the values through the clock network. If this attribute is not
present, ideal clocking is assumed. Set with set_propa-
gated_clock.
setup_uncertainty
Specifies a positive uncertainty from the edges of the ideal
clock waveform. Set with set_clock_uncertainty -setup.
Design Attributes
async_set_reset_q
Establishes the value (0 or 1) that should be assigned to the q
output of an inferred register if set and reset are both active
at the same time. To be used with async_set_reset_qn. Use
these attributes only if you have used the one_hot or one_cold
attributes/directives in your HDL description and your logic
library is written using pre-V3.0a syntax; or if your logic
library does not use a consistent convention for q and qn when
set and reset are both active. If a V3.0a or later syntax logic
library is used, then by default if set and reset are both
active at the same time Design Compiler will use the convention
of the selected logic library (target_library). Set with
set_attribute.
Note: If you are unsure whether or not your logic library uses
V3.0a syntax, ask your ASIC vendor.
async_set_reset_qn
Establishes the value (0 or 1) that should be assigned to the qn
output of an inferred register if set and reset are both active
at the same time. To be used with async_set_reset_q. Use these
attributes only if you have used the one_hot or one_cold
attributes/directives in your HDL description and your logic
library is written using pre-V3.0a syntax; or if your logic
library does not use a consistent convention for q and qn when
set and reset are both active. If a V3.0a or later syntax logic
library is used, then by default if set and reset are both
active at the same time Design Compiler will use the convention
of the selected logic library (target_library). Set with
set_attribute.
If you are unsure whether or not your logic library uses V3.0a
syntax, ask your ASIC vendor.
balance_registers
Determines whether the registers in a design are retimed during
compile. When true (the default value), compile invokes the
balance_registers command, which moves registers to minimize the
maximum register-to-register delay. Set this attribute to
false, or remove it, to disable this behavior.
Set with set_balance_registers.
If your design contains generic logic, you should ensure that
all components are mapped to cells from the library before set-
ting the balance_registers attribute.
boundary_optimization
Enables compile to optimize across hierarchical boundaries.
Hierarchy is ignored during optimization for designs with this
attribute set to true. Set with set_boundary_optimization .
default_flip_flop_type
Specifies the default flip-flop type for the current design.
During the mapping process, compile tries to convert all
unmapped flip-flops to this type. If compile is unable to use
this flip-flop, it maps these cells into the smallest flip-flop
possible. Set with set_register_type -flip_flop flip_flop_name.
default_flip_flop_type_exact
During the mapping process, compile converts unmapped flip-flops
to the exact flip-flop type specified here. Set with
set_register_type -exact -flip_flop flip_flop_name
default_latch_type_exact
Specifies the exact default latch type for the current_design.
During the mapping process, compile converts unmapped latches to
the exact latch type specified here. Set with
set_register_type -exact -latch latch_name.
design_type
Indicates the current state of the design and has the value fsm
(finite state machine), pla (programmable logic array), equation
(Boolean logic), or netlist (gates). This attribute is "read-
only" and cannot be set by the user.
dont_touch
Identifies designs that are to be excluded from optimization.
Values are true (the default) or false. Designs with the
dont_touch attribute set to true are not modified or replaced
during compile. Setting dont_touch on a design has an effect
only when the design is instantiated within another design as a
level of hierarchy; setting dont_touch on the top-level design
has no effect. Set with the set_dont_touch command.
flatten
When set to true, determines that a design is to be flattened
during compile. By default, a design is not flattened. Set
with the set_flatten command.
flatten_effort
Defines the level of CPU effort that compile uses to flatten a
design. Allowed values are low (the default), medium, or high.
Set with the set_flatten command.
flatten_minimize
Defines the minimization strategy used for logic equations.
Allowed values are single_output, multiple_output, or none. Set
with the set_flatten command.
flatten_phase
When true, allows logic flattening to invert the phase of out-
puts during compile. By default, logic flattening does not
invert the phase of outputs. Used only if the flatten attribute
is set. Set with set_flatten.
implementation
The implementation for each specified instance of the specified
component_type. Specifying the -default option removes this
attribute from all instances of the component type in the cur-
rent design. Set with set_jtag_implementation.
is_combinational
true if all cells of a design and all designs in its hierarchy
are combinational. A cell is combinational if it is non-sequen-
tial or nonthree-state and all of its outputs compute a combina-
tional logic function. The report_lib command will report such a
cell as not a black-box. This attribute is read-only; you cannot
set it.
is_dw_subblock
true if the object (a cell, a reference, or a design) is a DW
subblock that was automatically elaborated. This attribute is
"read-only" and cannot be set by the user.
NOTE: DW subblocks that are manually elaborated will not have
this attribute.
is_hierarchical
true if any of the cells of a design are not leaf cells (for
example, not from a logic library). This attribute is read-only
and cannot be set by the user.
is_mapped
true if all the non-hierarchical cells of a design are mapped to
cells in a logic library. This attribute is "read-only" and
cannot be set by the user.
is_sequential
true if any cells of a design or designs in its hierarchy are
sequential. A cell is sequential if it is not combinational (if
any of its outputs depend on previous inputs). This attribute
is read-only and cannot be set by the user.
is_synlib_module
true if the object (a cell, a reference, or a design) refers to
an unmapped module reference or if the object is (or refers to)
a design that was automatically elaborated from a synlib module
or a synlib operator. This attribute is "read-only" and cannot
be set by the user.
NOTE: synlib modules that are manually elaborated will not have
this attribute.
is_unmapped
true if any of the cells are not linked to a design or mapped to
a logic library. This attribute is read-only and cannot be set
by the user.
local_link_library
A string that contains a list of design files and libraries to
be added to the beginning of the link_library whenever a link
operation is performed. Set with set_local_link_library.
map_only
When set to true, compile will attempt to map the object exactly
in the target library, and will exclude the object from logic-
level optimization (flattening and structuring). The default is
false. Set with set_map_only.
max_area
A floating point number that represents the target area of the
design. compile uses it to calculate the area cost of the
design. The units must be consistent with the units used from
the logic library during optimization. Set with set_max_area.
max_capacitance
A floating point number that sets the maximum capacitance value
for input, output, or bidirectional ports, or designs. The
units must be consistent with those of the logic library used
during optimization. Set with set_max_capacitance.
max_total_power
A floating point number that specifies the maximum target total
power for the current_design. Total power is defined as the sum
of dynamic and leakage power. If this attribute is specified
more than once for a design, the latest value is used. Set with
set_max_total_power.
minimize_tree_delay
When true (the default value), compile restructures expression
trees in the current_design or in a list of specified designs,
to minimize tree delay. The value of this attribute overrides
the value of hlo_minimize_tree_delay. Set this attribute to
false for any designs that you do not wish to be restructured.
Set with set_minimize_tree_delay.
model_map_effort
Specifies the relative amount of CPU time to be used by compile
during modeling, typically for synthetic library implementa-
tions. Values are low, medium, and high, or 1, 2, and 3. If
model_map_effort is not set, the value of syn-
lib_model_map_effort is used. Set with the set_model_map_effort
command.
model_scale
A floating point number that sets the model scale factor for the
current_design. Set with set_model_scale.
optimize_registers
When true (the default value), compile automatically invokes the
Behavioral Compiler optimize_registers command to retime the
design during optimization. Setting the attribute to false dis-
ables this behavior. Your design cannot contain generic logic
at the instant optimize_registers is invoked during compile.
Set with set_optimize_registers.
part A string value that specifies the Xilinx part type for a design.
For valid part types, refer to the Xilinx XC4000 Databook. Set
with set_attribute.
port_is_pad
Indicates specified ports are to have I/O pads attached. The I/O
pads are added during insert_pads and automatically added during
compile. Set using set_port_is_pad.
resource_allocation
Indicates the type of resource allocation to be used by compile
for the current_design. Allowed values are none, indicating no
resource sharing; area_only, indicating resource sharing with
tree balancing without considering timing constraints;
area_no_tree_balancing, indicating resource sharing without tree
balancing and without considering timing constraints; and con-
straint_driven (the default), indicating resource sharing so
that timing constraints are met or not worsened. The value of
this attribute overrides the value of the variable
hlo_resource_allocation for the current_design. Set with
set_resource_allocation.
resource_implementation
Indicates the type of resource implementation to be used by com-
pile for the current_design. Allowed values are area_only,
indicating resource implementation without considering timing
constraints; constraint_driven, indicating resource implementa-
tion so that timing constraints are met or not worsened; and
use_fastest, indicating resource implementation using the
fastest implementation initially, unless all timing constraints
are met. If the fastest implementation has been selected ini-
tially later steps of the compile command will select components
with smaller area later in uncritical parts of the design. The
value of this attribute overrides the value of the variable
hlo_resource_implementation for the current_design. Set with
set_resource_implementation.
scan_element
Determines if sequential cells in the specified designs are
replaced by equivalent scan cells or designs during insert_scan.
Default is set to true. When set to false, sequential cells are
not replaced by equivalent scan cells. Set with set_scan_ele-
ment.
scan_latch_transparent
When set to true, makes specified designs transparent during
ATPG. For hierarchical cells, the effects apply hierarchically
to level-sensitive leaf cells. The set_scan_transparent command
sets the attribute; the remove_attribute command removes it.
share_cse
When true, the value of the environment variable hlo_share_com-
mon_subexpressions is used. The value of this attribute deter-
mines whether common subexpressions are shared during compile,
to reduce the cost of the design. Setting the attribute to false
overrides the hlo_share_common_subexpressions. Set with
set_share_cse.
structure
Determines if a design is to be structured during compile. If
true, adds logic structure to a design by adding intermediate
variables that are factored out of the design's equations. Set
with set_structure .
structure_boolean
Enables the use of Boolean (non-algebraic) techniques during the
structuring phase of optimization. This attribute is ignored if
the structure attribute is false Set with set_structure .
structure_timing
Enables timing constraints to be considered during the structur-
ing phase of optimization. This attribute is ignored if the
structure attribute is false. Set with set_structure .
ungroup
Removes a level of hierarchy from the current design by explod-
ing the contents of the specified cell in the current design.
Set with set_ungroup .
wired_logic_disable
When true, disables creation of wired OR logic during compile.
The default is false; if this attribute is not set, wired OR
logic will be created if appropriate. Set with
set_wired_logic_disable.
wire_load_model_mode
Determines which wire load model to use to compute wire capaci-
tance, resistance, and area for nets in a hierarchical design
that has different wire load models at different hierarchical
levels. Allowed values are top, which indicates to use the wire
load model at the top hierarchical level; enclosed, which indi-
cates to use the wire load model on the smallest design that
encloses a net completely; and segmented, which indicates to
break the net into segments, one within each hierarchical level.
In the segmented mode, each net segment is estimated using the
wire load model on the design that encloses that segment. The
segmented mode is not supported for wire load models on clus-
ters. If a value is not specified for this attribute, compile
searches for a default in the first library in the link path.
If none is found, top is the default. Set with set_wire_load.
xnfout_use_blknames
When true, the Synopsys XNF writer writes BLKNM XNF parameters
into the XNF netlist for your design when write -f xnf is
invoked. The default is false. The BLKNM XNF parameters convey
to the Xilinx place and route tools information, previously
placed on the db_design by replace_fpga, that indicates which
groupings of function generators are to be packed into CLB
cells. Set with set_attribute.
Library Cell Attributes
dont_touch
Identifies library cells to be excluded from optimization. Val-
ues are true (the default) or false. Library cells with the
dont_touch attribute set to true are not modified or replaced
during compile. Setting dont_touch on a hierarchical cell sets
the attribute on all cells below it. Set with set_dont_touch .
dont_use
Disables the specified library cells so that they are not added
to a design during compile. Set with set_dont_use .
formula
The attribute of the priority parameter for implementations in
synthetic libraries. The formula should evaluate to an integer
between 0 and 10. Set with set_impl_priority.
implementation
Specifies the implementation for the synthetic library cell
instances to use. When compile is run, the implementation you
specified is used if you set this attribute. The cells instances
must be defined in the synthetic library for this attribute to
work. Set with set_implementation.
no_sequential_degenerates
When true, disables mapping to versions of this latch or flip
flop that have some input pins connected to 0 or to 1. Set with
set_attribute. This attribute may also be set on the library
itself, and that value will apply as the default for all regis-
ters in the library which don't have the attribute set individu-
ally.
preferred
Specifies the preferred library gate to use during technology
translation when there are other gates with the same function in
the target library. Set with the set_prefer command.
scan When true, specifies that the instances of the library cell are
always replaced by equivalent scan cells during insert_dft.
When false, instances are not replaced. Set with set_scan.
scan_group
A user-defined string variable that allows you to specify to DFT
Compiler a preferred scan equivalent for a non-scan storage ele-
ment, when a library contains multiple scan equivalents. Typical
values are low, medium, and high, for low, medium, and high
drive strengths. However, you can define any string variable,
and it need not describe drive strength. The default behavior is
for DFT Compiler to attempt to choose a scan element that best
matches the electrical characteristics of the nonscan element;
for a more detailed explanation, refer to the DFT Compiler Scan
Synthesis User Guide. The matching of electrical characteristics
works well with the standard CMOS delay model, but is not accu-
rate with other delay models; scan_group provides a means for
you to specify an appropriate scan equivalent. Normally,
scan_group would be set by the ASIC vendor or library developer,
but can also be set by you. Consult your ASIC vendor before
attempting to set scan_group with set_attribute. For more infor-
mation about scan_group, refer to the DFT Compiler Scan Synthe-
sis User Guide.
set_id Allows for the value for the implementations in synthetic
libraries. Set with set_impl_priorities.
scan_element
Determines if specified designs are scan replaced by
insert_scan. Set using set_scan_element.
scan_latch_transparent
When true, makes the specified library cells transparent in
ATPG. For hierarchical cells, the effects apply hierarchically
to level-sensitive leaf cells. The set_scan_transparent command
sets the attribute; the remove_attribute command removes it.
sequential_bridging
When true, enables Design Compiler to take a multiplexed flip-
flop and bridge (that is, connect) the output to the input to
get a desired functionality. The default is false, so this
attribute must be set in order to enable the functionality.
Bridging is required for mapping in cases where there is no
flip-flop with internal feedback in the target library but one
is desired in the HDL. Set with set_attribute. This attribute
may also be set on the library itself, and that value will apply
as the default for all registers in the library which don't have
the attribute set individually.
NOTE: Setting this attribute to true can result in an increase
in run times and memory consumption for Design Compiler. The
increased run times depend on the number of flip-flops in the
target library or libraries for which this attribute has been
set.
Pin Attributes
actual_max_net_capacitance
actual_min_net_capacitance
A floating point number that specified the total calculated
capacitance of the net that is connected to the given pin. The
attributes are defined only for pins of leaf cell. The value of
these attributes is calculated upon request. These are "read-
only" attributes and they cannot be set by the user.
disable_timing
Disables timing arcs. This has the same effect on timing as not
having the arc in the library. Set with set_disable_timing.
max_slack
A floating point value representing the worst slack of
max_rise_slack and max_fall_slack.
max_fall_slack
A floating point value representing the worst slack at a pin for
falling maximum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
max_rise_slack
A floating point value representing the worst slack at a pin for
rising maximum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
min_slack
A floating point value representing the worst slack of
min_rise_slack and min_fall_slack.
min_fall_slack
A floating point value representing the worst slack at a pin for
falling minimum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated..
min_rise_slack
A floating point value representing the worst slack at a pin for
rising minimum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
max_fall_delay
A floating point value that specifies the maximum falling delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_max_delay.
max_rise_delay
A floating point value that specifies the maximum rising delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_max_delay.
min_fall_delay
A floating point value that specifies the minimum falling delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_min_delay.
min_rise_delay
A floating point value that specifies the minimum rising delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_min_delay.
hold_uncertainty
Specifies a negative uncertainty from the edges of the ideal
clock waveform. Affects all sequential cells in the transitive
fanout of this pin. Set with set_clock_uncertainty -hold.
observe_pin
Specifies the (internal) observe pin name of an LSI Logic scan
macrocell (LSI CTV only). This attribute is used by the
write_test command. Set with set_attribute .
pin_direction
Specifies the direction of a pin. Allowed values are in, out,
inout, or unknown. This attribute is read-only and cannot be
set by the user.
pin_properties
Lists valid EDIF property values to be attached to different
versions of the output pin. The EDIF property values correspond
to different output emitter-follower resistance values on the
output pin. For details about the use of this attribute, refer
to the Library Compiler Reference Manual, Chapter 6, "Defining
Cells." Set with set_attribute.
setup_uncertainty
Specifies a positive uncertainty from the edges of the ideal
clock waveform. Affects all sequential cells in the transitive
fanout of this pin. Set with set_clock_uncertainty -setup.
set_pin
Specifies the (internal) set pin name of an LSI Logic scan
macrocell (LSI CTV only). This attribute is used by the
write_test command. Set with set_attribute .
signal_type
Used to indicate that a pin or port is of a special type, such
as a clocked_on_also port in a master/slave clocking scheme, or
a test_scan_in pin for scan-test circuitry. Set with set_sig-
nal_type .
static_probability
A floating point number that specifies the percentage of time
that the signal is in the logic 1 state; this information is
used by report_power. If this attribute is not set,
report_power will use the default value of 0.5, indicating that
the signal is in the logic 1 state half the time. Set with
set_switching_activity.
test_assume
A string that represents a constant logic value to be assumed
for specified pins throughout test design rule checking by
check_test. "1", "one", or "ONE" specifies a constant value of
logic one; "0", "zero", or "ZERO" specifies a constant value of
logic zero. Use report_test -assertions for a report on objects
that have the test_assume attribute set. Set with
set_test_assume .
test_initial
A string that represents an initial logic value to be assumed
for specified pins at the start of test design rule checking and
fault simulation by check_test. "1", "one", or "ONE" specifies
an initial value of logic one; "0", "zero", or "ZERO" specifies
an initial value of logic zero. Use report_test -assertions for
a report on objects that have the test_initial attribute set.
Set with set_test_initial.
test_isolate
Indicates that the specified sequential cells, pins, or ports
are to be logically isolated and considered untestable during
test design rule checking by check_test. When this attribute is
set on a cell, it is also placed on all pins of that cell. Do
not set this attribute on a hierarchical cell. Use report_test
-assertions for a report on isolated objects. Set with
set_test_isolate.
Note: Setting this attribute suppresses the warning messages
associated with the isolated objects.
test_routing_position
Specifies the preferred routing order of the scan-test signals
of the identified cells. Set with set_test_routing_order .
toggle_rate
A positive floating point number that specifies the toggle rate;
that is, the number of zero-to-one and one-to-zero transitions
within a library time unit period. This information is used by
report_power; if this attribute is not set, report_power will
use the default value of 2*(static_probability)(1 - static_prob-
ability). The default will be scaled by any associated clock
signal (if one is available). Set with set_switching_activity.
true_delay_case_analysis
Specifies a value to set all or part of an input vector for
report_timing -true and report_timing -justify. Allowed values
are 0, 1, r (rise, X to 1), and f (fall, X to 0). Set with the
set_true_delay_case_analysis command.
Port Attributes
actual_max_net_capacitance
actual_min_net_capacitance
A floating point number that specified the total calculated
capacitance of the net connected to the given port. The value
of these attributes is calculated upon request. These are
"read-only" attributes and they cannot be set by the user.
connection_class
A string that specifies the connection class label to be
attached to a port or to a list of ports. compile, insert_pads,
and insert_dft will connect only those loads and drivers that
have the same connection class label. The labels must match
those in the library of components for the design, and must be
separated by a space. The labels universal and default are
reserved; universal indicates that the port can connect with any
other load or driver, and default is assigned to any ports that
do not have a connection class already assigned. Set with
set_connection_class.
dont_touch_network
When a design is optimized, compile assigns dont_touch
attributes to all cells and nets in the transitive fanout of
dont_touch_network clock objects. The dont_touch assignment
stops at the boundary of storage elements. An element is recog-
nized as storage only if it has setup or hold constraints. Set
with set_dont_touch_network .
driven_by_dont_care
Specifies that input port are driven by dont_care. Compile uses
this information to create smaller designs. After optimization,
the port connected to dont_care does not drive anything inside
the optimized design. Set with set_logic_dc.
driven_by_logic_one
Specifies that input ports are driven by logic one. compile
uses this information to create smaller designs. After opti-
mization, a port connected to logic one usually does not drive
anything inside the optimized design. Set with set_logic_one .
driven_by_logic_zero
Specifies that input ports are driven by logic zero. compile
uses this information to create smaller designs. After opti-
mization, a port connected to logic zero usually does not drive
anything inside the optimized design. Set with set_logic_zero .
driving_cell_dont_scale
When true, indicates not to scale the transition time on the
port using the driving cell. Otherwise the transition time will
be scaled by operating condition factors. Set with set_driv-
ing_cell.
driving_cell_fall
A string that names a library cell from which to copy fall drive
capability to be used in fall transition calculation for the
port. Set with set_driving_cell.
driving_cell_from_pin_fall
A string that names the driving_cell_fall input pin to be used
to find timing arc fall drive capability. Set with set_driv-
ing_cell.
driving_cell_from_pin_rise
A string that names the driving_cell_rise input pin to be used
to find timing arc rise drive capability. Set with set_driv-
ing_cell.
driving_cell_library_fall
A string that names the library in which to find the driv-
ing_cell_fall. Set with set_driving_cell.
driving_cell_library_rise
A string that names the library in which to find the driv-
ing_cell_rise. Set with set_driving_cell.
driving_cell_multiply_by
A floating point value by which to multiply the transition time
of the port marked with this attribute. Set with set_driv-
ing_cell.
driving_cell_pin_fall
A string that names the driving_cell_fall output pin to be used
to find timing arc fall drive capability. Set with set_driv-
ing_cell.
driving_cell_pin_rise
A string that names the driving_cell_rise output pin to be used
to find timing arc rise drive capability. Set with set_driv-
ing_cell.
driving_cell_rise
A string that names a library cell from which to copy rise drive
capability to be used in rise transition calculation for the
port. Set with set_driving_cell.
fall_drive
Specifies the drive value of high to low transition on input or
inout ports. Set with set_drive.
fanout_load
Specifies the fanout load on output ports. Set with
set_fanout_load .
load Specifies the load value on ports. The total load on a net is
the sum of all the loads on pins, ports, and wires associated
with that net. Set with set_load.
max_capacitance
A floating point number that sets the maximum capacitance value
for input, output, or bidirectional ports, and/or designs. The
units must be consistent with those of the logic library used
during optimization. Set with set_max_capacitance.
max_fall_delay
A floating point value that specifies the maximum falling delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_max_delay.
max_fanout
Specifies the maximum fanout load for the net connected to this
port. compile ensures that the fanout load on this net is less
than the specified value. Set with set_max_fanout .
max_rise_delay
A floating point value that specifies the maximum rising delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_max_delay.
max_slack
A floating point value representing the worst slack of
max_rise_slack and max_fall_slack.
max_fall_slack
A floating point value representing the worst slack at a pin for
falling maximum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
max_rise_slack
A floating point value representing the worst slack at a pin for
rising maximum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
min_slack
A floating point value representing the worst slack of
min_rise_slack and min_fall_slack.
min_fall_slack
A floating point value representing the worst slack at a pin for
falling minimum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
min_rise_slack
A floating point value representing the worst slack at a pin for
rising minimum path delays. This attribute is valid for any pin
that appears in a constrained path after timing has been
updated.
max_time_borrow
A floating point number that establishes an upper limit for time
borrowing; that is, it prevents the use of the entire pulse
width for level-sensitive latches. Units are those used in the
logic library. Set with set_max_time_borrow.
max_transition
Specifies the maximum transition time for the net connected to
this port. compile ensures that value. Set with set_max_tran-
sition .
min_capacitance
A floating point number that sets the minimum capacitance value
for input and/or bidirectional ports. The units must be consis-
tent with those of the logic library used during optimization.
Set with set_min_capacitance.
min_fall_delay
A floating point value that specifies the minimum falling delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_min_delay.
min_rise_delay
A floating point value that specifies the minimum rising delay
on ports, clocks, pins, cells, or on paths between such objects.
Set with set_min_delay.
setup_uncertainty
Specifies a positive uncertainty from the edges of the ideal
clock waveform. Affects all sequential cells in the transitive
fanout of this port. Set with set_clock_uncertainty -setup.
hold_uncertainty
Specifies a negative uncertainty from the edges of the ideal
clock waveform. Affects all sequential cells in the transitive
fanout of this port. Set with set_clock_uncertainty -hold.
model_drive
A non-negative floating point number that specifies the esti-
mated drive value on ports in terms of standard drives of the
current logic library. Set with set_model_drive.
model_load
A non-negative floating point number that specifies the esti-
mated load value on ports in terms of standard loads of the cur-
rent logic library. Set with set_model_load.
op_used_in_normal_op
Specifies that a scan-out port is also used in normal operation
(system mode). This attribute is used by the insert_dft com-
mand. Set with set_attribute.
Read-Only Attributes
design_type
Indicates the current state of the design and has the value fsm
(finite state machine), pla (programmable logic array), equation
(Boolean logic), or netlist (gates). This attribute cannot be
set by the user.
is_black_box
true if the reference is not yet linked to a design or is linked
to a design that doesn't have a functionality. This attribute
cannot be set by the user.
is_combinational
true if all cells of a design and all designs in its hierarchy
are combinational. A cell is combinational if it is non-
sequential or non-tristate and all of its outputs compute a com-
binational logic function. The report_lib command will report
such a cell as not a black-box. This attribute is read-only and
cannot be set by the user.
is_dw_subblock
true if the object (a cell, a reference, or a design) is a DW
subblock that was automatically elaborated. This attribute is
"read-only" and cannot be set by the user.
is_hierarchical
true if any of the cells of a design are not leaf cells (for
example, not from a logic library). This attribute cannot be
set by the user.
is_mapped
true if all the non-hierarchical cells of a design are mapped to
cells in a logic library. This attribute cannot be set by the
user.
is_sequential
true if any cells of a design or designs in its hierarchy are
sequential. A cell is sequential if it is not combinational.
This attribute cannot be set by the user.
is_synlib_module
true if the object (a cell, a reference, or a design) refers to
an unmapped module reference or if the object is (or refers to)
a design that was automatically elaborated from a synlib module
or a synlib operator. This attribute is "read-only" and cannot
be set by the user.
NOTE: synlib modules that are manually elaborated will not have
this attribute.
is_synlib_operator
true if the object (a cell or a reference) is a synthetic
library operator reference. This attribute is "read-only" and
cannot be set by the user.
is_test_circuitry
Set by insert_dft on the scan cells and nets added to a design
during the addition of test circuitry. This attribute cannot be
set by the user.
is_unmapped
true if any of the cells are not linked to a design or mapped to
a logic library. This attribute cannot be set by the user.
direction
Returns the direction of a pin or port. The value can be in,
out, inout, or unknown. For backward compatibility, the
attribute also supports an integer value, 1 for in, 2 for out,
or 3 for inout. This attribute cannot be set by the user.
pin_direction
Returns the direction of a pin. The value can be in, out, inout,
or unknown. This attribute cannot be set by the user. You can
also use the direction attribute to get the direction of the
pin.
port_direction
Returns the direction of a port. The value can be in, out,
inout, or unknown. This attribute cannot be set by the user.
You can also use the direction attribute to get the direction of
the port.
ref_name
The reference name of a cell. This attribute cannot be set by
the user.
Reference Attributes
dont_touch
Specifies that designs linked to a reference with this attribute
are excluded from optimization. Values are true (the default)
or false. Designs linked to a reference with the dont_touch
attribute set to true are not modified or replaced during com-
pile. Set with set_dont_touch .
is_black_box
true if the reference is not yet linked to a design or is linked
to a design that doesn't have a functionality. This attribute
is read-only and cannot be set by the user.
is_combinational
true if all the cells of the referenced design are combina-
tional. A cell is combinational if it is non-sequential or non-
tristate and all of its outputs compute a combinational logic
function. The report_lib command will report such a cell as not
a black-box. This attribute is read-only and cannot be set by
the user.
is_dw_subblock
true if the object (a cell, a reference, or a design) is a DW
subblock that was automatically elaborated. This attribute is
read-only and cannot be set by the user.
NOTE: DW subblocks that are manually elaborated will not have
this attribute.
is_hierarchical
true if the referenced design is not a leaf cell (for example,
not in a logic library). This attribute is read-only and cannot
be set by the user.
is_mapped
true if the reference is linked to a design, and all the non-
hierarchical cells of the referenced design are mapped to cells
in a logic library. This attribute is read-only and cannot be
set by the user.
is_sequential
true if all the cells of the referenced design are sequential.
A cell is sequential if it is not combinational (if any of its
outputs depend on previous inputs). This attribute is read-only
and cannot be set by the user.
is_synlib_module
true if the object (a cell, a reference, or a design) refers to
an unmapped module reference or if the object is (or refers to)
a design that was automatically elaborated from a synlib module
or a synlib operator. This attribute is read-only and cannot be
set by the user.
NOTE: synlib modules that are manually elaborated will not have
this attribute.
is_synlib_operator
true if the object (a cell or a reference) is a synthetic
library operator reference. This attribute is read-only and
cannot be set by the user.
is_unmapped
true if any of the non-hierarchical cells of the referenced
design are not mapped to cells in a logic library, or if the
reference is not yet linked to a design. This attribute is
read-only and cannot be set by the user.
scan When true, specifies that cells of the referenced design are
always replaced by equivalent scan cells during insert_dft.
When false, cells of the design are not replaced. Set with
set_scan .
scan_chain
Includes the specified cells of the referenced design in the
scan-chain whose index is the value of this attribute. Set with
the set_scan_chain command.
scan_element
Determines if specified designs are scan replaced by
insert_scan. Set using set_scan_element.
scan_latch_transparent
When true, makes the specified references transparent in ATPG.
For hierarchical cells, the effects apply hierarchically to
level-sensitive leaf cells. The specified library cell cannot be
overwritten. Set with set_scan_transparent; remove with
remove_attribute.
ungroup
Specifies that all designs linked to a reference with this
attribute are ungrouped (levels of hierarchy represented by
these design cells are removed) during compile. Set with
set_ungroup .
SEE ALSO
get_attribute(2)
remove_attribute(2)
set_attribute(2)
power_attributes(3)
Version S-2021.06
Copyright (c) 2021 Synopsys, Inc. All rights reserved.