DIGITAL INTEGRATED CIRCUITS DESIGN LAB

LIST OF EXPERIMENTS:

PART-A

Write the Code using Verilog and simulate the following:

1   Write structural and dataflow Verilog HDL models for

4-bit ripple carry adder.

1.2          4-bit carry Adder – cum Subtractor.

1.3          2-digit BCD adder / subtractor.

1.4          4-bit carry look ahead adder

1.5          4-bit comparator

2   Write a Verilog HDL program in behavioural model for

2.1          8:1 multiplexer

2.2          3:8 decoder

2.3          8:3 encoder

2.4          8-bit parity generator and checker

3   Write a Verilog HDL program in Hierarchical structural model for

3.1          16:1 multiplexer realization using 4:1 multiplexer

3.2          3:8 decoder realization through 2:4 decoder

3.3          8-bit comparator using 4-bit comparators and additional logic

4   Write a Verilog HDL program in behavioural model for

4.1          D-FF,

4.2          T-FF and

4.3          JK-FF,

4.4          shift registers and

4.5          counters.

5   Write a Verilog HDL program in structural and behavioural models for

5.1          8 bit asynchronous up-down counter

5.2          8 bit synchronous up-down counter

6   Write a Verilog HDL program for 4-bit sequence detector through Moore state machines

7   Write a Verilog HDL program for 4-bit sequence detector through Mealy state machines

PART-B

8   Transistor Level implementation of CMOS circuits using VLSI CAD tool

8.1  Basic Logic Gates:

8.1.1        Inverter,

8.1.2        NAND and

8.1.3        NOR

8.2  Half Adder and Full Adder

8.3  2:1 Multiplexer and 4:1 Multiplexer using 2:1 Multiplexer

8.4  one bit comparator and four-bit magnitude comparator using one bit comparator

8.5  Implement the Layout of CMOS Inverter.

8.6  Implement the Layout of CMOS NAND.

Note:

1.       A total of 10 experiments must be completed in the semester.

2.       Minimum of 5 experiments from Part-A and 5 from Part-B is compulsory.