About TEAM
[PROCESS GROUP]
Device Characterization: H/W fabrication & measurement & analysis
High-k gate stack : Al2O3, HfO2, TiO2, bi-layer structure
Electrical properties : TLM, leakage current, Id-Vg, Id-Vd, C-V (f-Split, Hysteresis), Polarization, GIDL, noise(1/f, RTS), reliability(HCI, BTI, TDDB), parasitic RC breakdown and intrinsic channel properties (Cinv, mobility, Vinj) extraction, cryogenic
Structural properties : TEM, SEM, SIMS, XPS
Trap analysis : interface trap Nit extraction from C-V, border trap Not extraction from 1/f noise, trap location analysis using RTS noise
Fabrication : deposition(ALD, sputerring, CVD), etching, photolithography, diffusion
Process Integration
Next-generation devices : Ferroelectrics, Racetrack memory
Process technology (1) : Triple-beam laser spike annealing
Process technology (2) : Atomic layer deposition (ALD)
Process technology (3) : Sputtering
Layout & Test pattern
Device Fabrication: Silicon
Full process scheme(Fin/PC/SD/RMG/RPG/CNT) of 7/10 nm node bulk FinFETs
Experience on 300 mm Silicon wafer processing: FinFET and advanced node
TCAD virtual FAB-based 3D device process and integration
Unit process simulation such as IMPLANT/DIFFUSION/ANNEAL/EPI for process guidelines