About TEAM
[LOGIC GROUP]
Next-Generation Device TCAD Simulation Framework
Sub-3-nm node benchmarking & tech definition along with scaled devices
(FinFET, Gate-all-around FET (Nanosheet, Nanowire), Vertical FET, Complementary FET, III-V FET)
Quantitative DC/AC/RF performance benchmarking and transistor design optimization: PPA (Performance/Power/Area) analysis
TCAD simulation dealing with the issues that can be encountered in fabricating scaled devices
Device Measurement, Modeling, and Characterization
Electrical measurement of advanced CMOS devices including GAA FET, FinFET, NCFET, etc.: DC (I-V), AC (C-V), noise (fast I-V measurement), cryogenic (I-V and C-V under 77 K).
Physical compact models: BSIM4, BSIM-CMG, Virtual-Source model using Verilog-A, ML-based artificial compact model.
Characterization of advanced device: Carrier transport (mobility, scattering, ballistic mobility and velocity, velocity saturation), quantum confinement effect, variability, electrostatics, parasitic components, etc.
Diverse standard cell (AND2x1, INVx1…) and SRAM designs and their PPA analysis
Designing both FS-PDN (power delivery network) and BS-PDN (PV, BPR, BSC)
Designing monolithic 3D (M3D) cell structure