Conferences
International Conferences
70. S. Lee, J. Jeong, S. Lee, J. Lee, J. Lim, Y. Ahn and R.-H. Baek*, "Channel Trimming Process to Improve Electro-thermal Characteristics for Sub 3-nm Node Nanosheet Field-Effect Transistors with Laser Spike Annealing," Extended Abstracts of the 2023 International Conference on Solid State Devices and Materials (SSDM 2023), Nagoya, Japan, Sep. 5-8, 2023.
69. J. Jeong, S. Lee, S. Lee, J. Lee, J. Lim and R.-H. Baek*, "Holistic Analysis of Asymmetry in Vertical Silicon Gate-all-around Nanosheet FETs," Extended Abstracts of the 2023 International Conference on Solid State Devices and Materials (SSDM 2023), Nagoya, Japan, Sep. 5-8, 2023.
68. J. Lee, J. Jeong, S. Lee, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens-Yu, D. Greenlaw and R.-H. Baek*, “Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications,” Symposium on VLSI Technology and Circuits (VLSI-T), Kyoto, Japan, June. 11-16, 2023.
67. H. You, J. An, K. Nam, B. Kang, J. Park, N. Lee, S. Lee, and R.-H. Baek*, “Forward Body Bias Technique in DRAM Peripheral Transistor at Cryogenic Temperature for Quantum Computing Applications,” The 7th Electron Devices Technology and Manufacturing (EDTM 2023) conference, Seoul, Korea, Mar. 7-10, 2023 (Best Student Paper Award).
66. J. Lim, J. Jeong, J. Lee, S. Lee, S. Lee, and R.-H. Baek*, “Investigation of Self-Heating Effect in Forksheet FETs for Sub-3-nm Node,” The 7th Electron Devices Technology and Manufacturing (EDTM 2023) conference, Seoul, Korea, Mar. 7-10, 2023.
65. S. Lee, J. Jeong, J.-S. Yoon, S. Lee, J. Lee, J. Lim, and R.-H. Baek*, “Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs,” The 7th Electron Devices Technology and Manufacturing (EDTM 2023) conference, Seoul, Korea, Mar. 7-10, 2023 (Best Student Paper Award).
64. S. Kim, M. Kwon, H.-W Lee, K. Kim, B. Kang, H. Choo, J.-H Park, R.-H Baek, H. Hwang, and B. Lee*, “Study of continuous-wave RGB laser annealing for the activation of phosphorus/boron-doped Si deep junction with high scan speed,” The 7th Electron Devices Technology and Manufacturing (EDTM 2023) conference, Seoul, Korea, Mar. 7-10, 2023.
63. B. Kang, J. Park, J. Hwang, S. Lee, H. Shin, J. An, H. You, S.-M. Ahn, S. Jeon, and R.-H. Baek*, “Development of MFMIS Gatestack with Thick Hafnium Zirconium Oxide (HZO) for Nonvolatile Memory Application,” The 7th Electron Devices Technology and Manufacturing (EDTM 2023) conference, Seoul, Korea, Mar. 7-10, 2023 (Best Student Paper Award).
62. J. Lim, J. Jeong, J. Lee, S. Lee, S. Lee, and R.-H. Baek*, "Characterization of Coupling Effect between P/NMOS by Source/Drain Recess Depth Variations in sub-3-nm Node Silicon Forksheet FETs," NANO KOREA 2022, Jul. 6-8, 2022.
61. S. Heo, J. Lee, S. Lee, S. Lee, C. Lee, R.-H. Baek, and H. Hwang*, "High-Speed Ternary CMOS Inverter by Monolithic Integration of NbO2 Threshold Switch with MOSFET," IEEE International Electron Devices Meeting 2021 (IEDM 2021), Dec. 11-16, 2021.
60. K. Nam, C. Park, J.-S. Yoon, H. Yun, H. Jang, K. Cho, H. Kang, M. Park, H. Oh, J. Sim, and R.-H. Baek*, "Optimal Energetic Trap Distribution of Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using Machine Learning Methodology," Extended Abstracts of the 2021 International Conference on Solid State Devices and Materials (SSDM 2021), ALL-VIRTUAL conference, Sep 6-9, 2021.
59. J. An, K. Choi, B. Kang, R.-H. Baek*, “Interface Trap Curing Effects on High-k Gate Stack (Al/Al2O3/Si-sub) by Rapid Thermal Anneal (RTA),” NANO KOREA 2020, Jul. 1-3, 2020.
58. H. Yun, J.-S. Yoon, H. Choi, R.-H. Baek*, “Neural Network Based 14-nm Node Fully-Depleted FET Design for AC Applications of SoC and 3DIC,” NANO KOREA 2020, Jul. 1-3, 2020.
57. B. Kang, K. Choi, J. An, R.-H. Baek*, “Electrical and Dielectric Properties of TiO2 Based MIS Capacitor,” NANO KOREA 2020, Jul. 1-3, 2020.
56. J. Lee, J.-S. Yoon, J. Jeong, S. Lee, R.-H. Baek*, “SRAM Performance Variations Induced by Source/Drain Mole Fraction Change of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors,” NANO KOREA 2020, Jul. 1-3, 2020.
55. J. Jeong, J.-S. Yoon, S. Lee, J. Lee, R.-H. Baek*, “TSV-to-Transistor Noise Coupling Characterizations for Sub 5-nm Node Fin- and Nanosheet FETs in 3D-IC,” NANO KOREA 2020, Jul. 1-3, 2020.
54. H. Yun, J.-S. Yoon, J. Jeong, S. Lee, H.-C. Choi, and R.-H. Baek*, “Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications,” The 4th Electron Devices Technology and Manufacturing (EDTM 2020) conference, Penang, Malaysia, Mar. 12-15, 2020.
53. J.-S. Yoon, S. Lee, J. Jeong, R.-H. Baek*, “Critical dimension variations of sub 5-nm node fin and nanosheet FETs,” NANO KOREA 2019, Jul. 2-5, 2019.
52. J. Jeong, J.-S. Yoon, S. Lee, R.-H. Baek*, “Impact of Thermo-Mechanical Stress Induced by Through-Silicon Vias on Performance Variations of 5-nm Node Si-Nanosheet FETs,” NANO KOREA 2019, Jul. 2-5, 2019.
51. S. Lee, J.-S. Yoon, J. Jeong, J. Lee, R.-H. Baek*, “Comparison of virtual source velocity and apparent mobility in shrunk Lg=15 nm n/p-SNWFETs with various channel diameters,” NANO KOREA 2019, Jul. 2-5, 2019.
50. C. Park, K. Nam, H. Jang. R.-H. Baek*, "Extensive Analysis of Incremental Step Programming Pulse (ISPP) Slope Degradation in NAND Flash Memory," NANO KOREA 2019, Jul. 2-5, 2019.
49. H. Jang, H. Oh, C. Park, R.-H. Baek*, "Scalability of OTS Integrated PCM for 3-D Stackable Cross-point Array Structure Using TCAD Simulation," NANO KOREA 2019, Jul. 2-5, 2019.
48. J. Jeong, J.-S. Yoon, S. Lee, R.-H. Baek*, “The Effects of Realistic U-shaped Source/Drain on DC/AC Performances of Silicon Nanosheet FETs for Sub 5-nm Node SoC Applications,” The 3rd Electron Devices Technology and Manufacturing (EDTM 2019) conference, Singapore, Mar. 12-15, 2019.
47. Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, and R.-H. Baek, “Nanosheet Number and Width Optimization of Multi Stacked Si-NanoSheet FET for 7-nm Node SoC Application ” Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM 2018), Tokyo, Japan, Sep 9-13, 2018.
46. H. Oh, J. Kim, R.-H. Baek, and J.-S. Lee “Vth variation of string SONOS NAND Flash depending on single grain boundary and stored electron charges in an adjacent cell” Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM 2017), Sendai, Japan, Sep 19-22, 2017.
45. J.-S. Lee, S. Jeong, D. Kim, C. Park, R.-H. Baek, and B. Jin, "Improving DMMP(Salin simulant) Sensing Characteristics of TFQ Functionalized Graphene Chemiresistive Sensors", in 17th IEEE IEEE-NANO, Pitts Marriott City Center, USA, July 25-28, 2017.
44. D.-H. Kim, J. A. del Alamo, D. A. Antoniadis, M. Urteaga, B. Brar, T.-W. Kim, R.-H. Baek, P. D. Kirsch, W. Maszara, H.-M. Kwon, C.-S. Shin, W.-K. Park, Y. D. Cho, S. C. Shin, D. H. Ko, and K.-S. Seo, “High-Performance III-V Devices for Future Logic Applications,” IEEE International Electron Devices Meeting 2014 (IEDM 2014), San Francisco, USA, Dec. 15-17, 2014.
43. J. H. Hong, S. H. Lee, Y. R. Kim, E. Y. Jeong, J. S. Yoon, J. S. Lee, R.-H. Baek, and Y.-H. Jeong, “Impact of High-k Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node,” Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials (SSDM 2014), Tsukuba, Japan, Sep. 8-11, 2014.
42. E.-Y. Jeong, M. J. Deen, C.-H. Chen, R.-H. Baek, J.-S. Lee and Y.-H. Jeong, “Physical DC and Thermal Noise Models of 18 nm DG Junctionless pMOSFETs,” Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials (SSDM 2014), Tsukuba, Japan, Sep. 8-11, 2014.
41. R.-H. Baek, T.-W. Kim, T. Michalak, C. Borst, C. Shin, W. Park, S.-C. Song, G. Yeap, R. Hill, C. Hobbs, W. Maszara D.-H. Kim and P. Kirsch, "Electrostatics and Performance Benchmarking using all Types of III-V Multi-Gate FinFETs for sub 7nm Technology Node Logic Application," International Symposium on VLSI Technology Digest (VLSI 2014), Hawaii, USA, Jun. 9-13, 2014. (Oral presentation)
40. C. Y. Kang, R.-H. Baek, T.W. Kim, D. Ko, D.H. Kim, T. Michalak, C. Borst, D. Veksler, G. Bersuker, R. Hill, C. Hobbs, and P.D. Kirsch, "Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node," IEEE International Electron Devices Meeting 2013 (IEDM 2013), Washington, USA, Dec. 9-11, 2013.
39. T.-W. Kim, D.-H. Kim, D. H. Koh, H. M. Kwon, R.-H. Baek, D. Veksler, C. Huffman, K. Matthews, S. Oktyabrsky, A. Greene, Y. Ohsawa, A. Ko, H. Nakajima, M. Takahashi, T. Nishizuka, H. Ohtake, S.K. Banerjee, S.-H. Shin, D.H. Ko, C. Kang, D. Gilmer, R.J.W. Hill, W. Maszara, C. Hobbs, and P.D. Kirsch, "Sub-100 nm InGaAs Quantum-Well (QW) MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for Low-Power Logic Applications," IEEE International Electron Devices Meeting 2013 (IEDM 2013), Washington, USA, Dec. 9-11, 2013.
38. R. T. P. Lee, R. J. W. Hill, W. Y. Loh, R.-H. Baek, S. Deora, K. Matthews, C. Huffman, K. Majumdar, T. Michalak, C. Borst, P.Y. Hung, C.-H. Chen, J.-H. Yum, T.-W. Kim, C.Y. Kang, W-E. Wang, D.-H. Kim, C. Hobbs, and P.D. Kirsch, "VLSI Processed InGaAs on Si MOSFETs with Thermally Stable, Self-Aligned Ni-InGaAs Contacts Achieving: Enhanced Drive Current and Pathway Towards a Unified S/D Contact Module," IEEE International Electron Devices Meeting 2013 (IEDM 2013), Washington, USA, Dec. 9-11, 2013.
37. C.-W. Sohn, C. Y. Kang, M. D. Ko, R.-H. Baek, C.-H. Park, S.-H. Kim, E.-Y. Jeong, J. S. Lee, P. Kirsch, R. Jammy, J. C. Lee, and Y.-H. Jeong, "Effects of fin height of tapered FinFETs on the sub-22nm System on Chip (SoC) application using TCAD simulation" International Symposium on VLSI-TSA, Hsinchu, Taiwan, Apr. 22-24, 2013.
36. C. Y. Kang, C.-W. Sohn, R.-H. Baek, C. Hobbs, P. Kirsch, and R. Jammy, "Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology," International Symposium on VLSI Technology Digest (VLSI 2013), Kyoto, Japan, Jun. 10-13, 2013.
35. C.-H. Park, M.-D. Ko, K.-H. Kim, J.-H. Hong, R.-H. Baek, J.-S. Yoon, J.-S. Lee, and Y.-H. Jeong, “Extraction of Series Resistance on Junctionless and Inversion-mode nanowire FET through the Method based on Y-function,” in international Conference on Device Research Conference (DRC 2013), U of Notre Dame, USA, pp. 225-226.
34. R.-H. Baek, C. Y. Kang, A. Kumar, C.-W. Sohn, T. Michalak, C. Borst, C. Hobbs, P. Kirsch, and R. Jammy, “Comprehensive Study of Process-Induced Device Performance Variability and its Optimization for 14 nm Technology Node Bulk FinFETs,” in international Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2012), Denver, USA, Sep. 5-7, 2012, pp. 105-108. (Oral presentation)
33. C.-W. Sohn, C. Y. Kang, R.-H. Baek, P. Kirsh, R. Jammy, M.-D. Ko, D.-Y. Choi, H. C. Sagong, E.-Y. Jeong, C.-K, Baek, J.-S. Lee, and Y.-H. Jeong, "Modeling and Analysis of the Parasitic Series Resistance in Raised Source/Drain FinFETs with Polygonal Shaped Epitaxy," in international Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2012), Denver, USA, Sep. 5-7, 2012, pp. 288-291.
32. I. Ok, K.-W.Ang, C. Hobbs, R.-H. Baek, C. Y. Kang, J. Snow, P. Nunan, S. Nadahara, P. Kirsch, and R. Jammy, “Conformal, low-damage shallow junction technology (Xj~5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node,” 12th International Workshop on Junction Technology (IWJT), May. 14-15, 2012, pp. 29-34.
31. C.-W. Sohn, C. Y. Kang, R.-H. Baek, D. Y. Choi, H. C. Sagong, E. Y. Jeong, J. S. Lee, P. Kirsch, R. Jammy, J. Lee, and Y. H. Jeong, "Comparative Study of Geometry-dependent Capacitances of Planar FETs and Double-Gate FinFETs: Optimization and Process Variation," International Symposium on VLSI-TSA, Hsinchu, Taiwan, Apr. 23-25, 2012.
30. R.-H. Baek, M.-D. Ko, S.-H. Lee, C.-K. Baek, K. H. Yeo, D.-W. Kim, J.-S. Lee, D. M. Kim, and Y.-H. Jeong, “Analysis of Parasitic Bottom Capacitance in n- and p-type Si-Nanowire Field Effect Transistors on Bulk,” in 11th IEEE-NANO 2011, Portland, USA, Aug. 15-19, 2011, pp. 139-143. (Oral presentation)
29. M. D. Ko, S. H. Lee, R.-H. Baek, C. H. Park, C. W. Sohn, C. K. Baek, J. S. Lee, Y. H. Jeong, "Analysis of Bottom Channel Effect in Silicon Nanowire FET based on Bulk-Silicon: Reduction of Parasitic Capacitance caused by SiGe layer," 2011 International Conference on Solid State and Device Materials(SSDM), Nagoya, Japan, Sep. 28-30, 2011.
28. Y. R. Kim, S. H. Lee, C. K. Baek, R.-H. Baek, K. H. Yeo, D. W. Kim, J. S. Lee, and Y. H. Jeong, "Reliable Extraction of Series Resistance in Silicon Nanowire FETs Using Y-function Technique," 2011 IEEE Nanotechnology Materials and Devices Conference, JeJu island, Korea, Oct. 19-21, 2011.
27. R.-H. Baek, C. K. Baek, S.-H. Lee, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, D.-W. Kim, J.-S. Lee, Dae M. Kim, and Y. H. Jeong, “C-V Characteristics and Analysis of Undoped Gate-All-Around Nanowire FET Array,” Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials (SSDM 2010), Tokyo, Japan, Sep. 21-24, 2010, pp. 1277-1278. (Oral presentation)
26. R.-H. Baek, C. K. Baek, H.-S. Choi, H. C. Sagong, S.-H. Lee, G.-B. Choi, S. H. Song, C.-H. Park, J.-S. Lee, Y. Y. Yeoh, K. H. Yeo, D.-W. Kim, Kinam Kim, Dae M. Kim, and Y.-H Jeong “Characteristics of Gate-All-Around Si-NWFET, including Rsd, Cylindrical Coordinate Based 1/f Noise and Hot Carrier Effects,” in IEEE IRPS(International Reliability Physics Symposium) 2010, Anaheim CA, USA, May. 2-6, 2010, pp.94-98. (Oral presentation)
25. Y. H. Jeong, R.-H. Baek, S.-H. Lee, C.-K. Baek, and Dae M. Kim, “Characteristics and Modeling of Si-nanowire FETs (Invited paper),” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010), Shanghai, China, Nov. 1-4, 2010.
24. Y. H. Jeong, R.-H. Baek, C.-K. Baek, K. H. Yeo, D.-W. Kim, J. Y. Chung, and Dae M. Kim, “Comparative Study of C-V Characteristics in Si-NWFET and MOSFET (Invited paper),” IEEE Nanotechnology Materials and Devices Conference (NMDC 2010), Monterey, CA, USA, Oct. 12-15, 2010.
23. D. Y. Choi, R.-H. Baek, and Y. H. Jeong, "Low Frequency Noise Analysis in Hfo2/SiON Gate Stack nMOSFETs With Different Interfacial Layer Thickness," 30th International Conference on the Physics of Semiconductors, Seoul, Korea, Jul. 25-30, 2010.
22. D. Y. Choi, C. W. Sohn, H. C. Sagong, M. S. Park, K. T. Lee, R.-H. Baek, C. Y. Kang, and Y. H. Jeong, "Low-Frequency Noise Behavior of La-Doped Hf-Based Dielectric nMOSFETs," 2010 International Conference on Solid State Devices and Materials, Tokyo, Japan, Sep. 22-24, 2010.
21. R.-H. Baek, C. K. Baek, S.-W. Jung, Y. Y. Yeoh, D.-W. Kim, J.-S. Lee, Dae M. Kim, and Y. H. Jeong, "Series Resistance Behavior Extracted from Silicon Nanowire Transistors Using the Y-function Technique," 2009 International Conference on Solid State Devices and Materials (SSDM 2009), Sendai, Japan, Oct. 6-9, 2009, pp. 1108-1109. (Oral presentation)
20. G. B. Choi, H. C. Sagong, K. T. Lee, M. S. Park, H. S. Choi, S. H. Song, R.-H. Baek, C. H. Park, S. H. Lee, J. S. Lee, C. Y. Kang, H-H. Tseng, R. Jammy, and Y. H. Jeong, "Impact of Dipole-induced Dielectric Relaxation on High-frequency Performance in La-incorporated HfSiON/Metal Gate nMOSFET," IEEE International Electron Devices Meeting 2009 (IEDM 2009), Baltimore, USA, Dec. 7-9, 2009.
19. H. C. Sagong, K. T. Lee, C. Y. Kang, G. B. Choi, H. S. Choi, R.-H. Baek, M. S. Park, S. W. Jung, and Y. H. Jeong, "RF Performance Degradation in 100-nm Metal Gate/High-k Dielectric nMOSFET by Hot Carrier Effects," IEEE European Solid-State Device Research Conference, Athens, Greece, Sep. 14-18, 2009.
18. S. H. Song, M. S. Park, K. T. Lee, H. S. Choi, G. B. Choi, R.-H. Baek, H. C. Sagong, S. W. Jung, C. Y. Kang, B. Wu, Y. H. Jeong, "Effects of High Pressure Hydrogen Anneal Process on Performance and Reliability in HfO2/SiO2 Dielectric with Contact Etch Stop Layer Stressor," IEEE Nanotechnology Materials and Devices Conference, Traverse, Michigan, USA, Jun. 2-5, 2009.
17. M. S. Park, K. T. Lee, S. H. Hong, S. H. Song, G. B. Choi, R.-H. Baek, H. S. Choi, H. C. Sagong, S. W. Jung, C. Y. Kang, B. Woo, and Y. H. Jeong, "High Pressure Hydrogen Annealing Effect of CESL Nitride Stressor MOSFETs with Metal Gate/High-k Dielectric on the Performance and Reliability," IEEE Nanotechnology Materials and Devices Conference, Traverse, Michigan, USA, Jun. 2-5, 2009.
16. J. C. Kim, K. T. Lee, S. H. Song, S. H. Hong, M. S. Park, H. S. Choi, G. B. Choi, R.-H. Baek, H. C. Sagong, S. W. Jung, C. Y. Kang and Y. H. Jeong, "Reliability of HfO2/SiO2 Dielectric with Strain Engineering using CESL Stressor," 2009 IEEE International Reliability Physics Symposium, Montreal, Canada, Apr. 26-30, 2009.
15. H. C. Sagong, K. T. Lee, S. H. Hong, H. S. Choi, G. B. Choi, R.-H. Baek, S. H. Song, M. S. Park, J. C. Kim, S. W. Jung, C. Y. Kang, and Y. H. Jeong, "RF and Hot Carrier Effects in metal gate/high-k Dielectric nMOSFETs at cryogenic temperature," 2009 IEEE International Reliability Physics 4Symposium, Montreal, Canada, Apr. 26-30, 2009.
14. G. B. Choi, S. H. Hong, H. S. Choi, R.-H. Baek, K. T. Lee, M. S. Park, S. H. Song, J. C. Kim, H. C. Sagong, H. Takeuchi, B. H. Lee, C. Y. Kang, and Y. H. Jeong, "Effective Carrier Mobility Extraction Based on RF Modeling for Highly Leaky MOSFET Devices with Short Channel Length and Small Area," 7th Spanish Conference on Electron Devices, Santiago de Compostela, Spain, 11-13 February, 2009, pp. 263-264.
13. R.-H. Baek, G. B. Choi, H.-S. Kang, S.-W. Jung, and Y. H. Jeong, "A Novel Series-resistance Extraction Method for Nano-scaled nMOSFETs Considering Mobility Degradation due to Vbs," IEEE Nanotechnology Materials and Devices Conference 2008 (NMDC 2008), Kyoto, Japan, Oct. 20-22, 2008.
12. G. B. Choi, S. H. Hong, H. S. Choi, R.-H. Baek, K. T. Lee, M. S. Park, S. H. Song, J. C. Kim, H. C. Sagong, and Y. H. Jeong, "Novel Extrinsic Series Resistance Extraction Methodology for Nanoscale MOSFETs," IEEE International RF and Microwave Conference (RFM 2008), Kuala Lumpur, Malaysia, Dec. 2-4, 2008.
11. J. C. Kim, K. T. Lee, S. H. Song, S. H. Hong, M. S. Park, H. S. Choi, G. B. Choi, R.-H. Baek, H. C. Sagong, S. W. Jung, C. Y. Kang and Y. H. Jeong, "Reliability of HfO2/SiO2 Dielectric with Strain Engineering using CESL Stressor," IEEE Nanotechnology Materials and Devices Conference 2008 (NMDC 2008), Kyoto, Japan, Oct. 20-22, 2008.
10. M. S. Park, K. T. Lee, G. B. Choi, S. H. Hong, H. S. Choi, R.-H. Baek, S. H. Song, J. C. Kim, H. C. Sagong, S. W. Jung, H. D. Lee, and Y. H. Jeong, "The Performance of HfSiON/TiN Gate Stack MOSFETs for 45 nm Node LSTP Application Using Conventional Fabrication Process," IEEE Nanotechnology Materials and Devices Conference 2008 (NMDC 2008), Kyoto, Japan, Oct. 20-22, 2008.
9. S. H. Song, J. C. Kim, K. T. Lee, S. H. Hong, M. S. Park, G. B. Choi, H. S. Kim, R.-H. Baek, H. C. Sagong, S. W. Jung, C. Y. Kang, and Y. H. Jeong, "Gate-Induced Drain Leakage (GIDL) Performance of Strain Engineering using CESL Stressor with High-k gate dielectric," IEEE Nanotechnology Materials and Devices Conference 2008 (NMDC 2008), Kyoto, Japan, Oct. 20-22, 2008.
8. G. B. Choi, S. H. Hong, H. S. Choi, R.-H. Baek, K. T. Lee, M. S. Park, S. H. Song, J. C. Kim, H. C. Sagong, S. W. Jung, H. Takeuchi, B. H. Lee, C. Y. Kang, H. D. Lee, and Y. H. Jeong, "Effective Mobility Extraction Methodology Using RF Modeling Scheme for Leaky MOSFET with Short Channel Length and Small Area," IEEE Nanotechnology Materials and Devices Conference 2008 (NMDC 2008), Kyoto, Japan, Oct. 20-22, 2008.
7. S. H. Hong, K. T. Lee, J. C. Kim, H. S. Choi, G. B. Choi, R.-H. Baek, M. S. Park, S. H. Song, H. C. Sagong, S. W. Jung, C. Y. Kang, and Y. H. Jeong, "Temperature dependent performances of nMOSFET with HfLaSiO gate dielectric," IEEE Nanotechnology Materials and Devices Conference 2008 (NMDC 2008), Kyoto, Japan, Oct. 20-22, 2008.
6. G. B. Choi, S. H. Hong, H. S. Choi, R.-H. Baek, K. T. Lee, M. S. Park, S. H. Song, J. C. Kim, H. C. Sagong, C. Y. Kang, B. H. Lee, G. Bersuker, H. H. Tseng, R. Jammy, S. W. Jung, and Y. H. Jeong, "New Multifrequency Capacitance Extraction Methodology for Leaky MOS Capacitor with High-k Dielectric and Metal Gate," 5th International Symposium on Advanced Gate Stack Technology (ISAGST 2008), Austin, USA, Sep. 29 - Oct. 1, 2008.
5. S. H. Hong, K. T. Lee, G. B. Choi, H. S. Choi, R.-H. Baek, M. S. Park, S. H. Song, J. C. Kim, H. C. Sagong, S. W. Jung, C. Y. Kang, G. Bersuker, H. H. Tseng, R. Jammy, B. H. Lee, and Y. H. Jeong, "Cryogenic RF Characteristics of HfO2-Gated nMOSFET," 5th International Symposium on Advanced Gate Stack Technology (ISAGST 2008), Austin , USA, Sep. 29 - Oct. 1, 2008.
4. K. T. Lee, C. Y. Kang, H. S. Choi, S. H. Hong, G. B. Choi, J. C. Kim, S. H. Song, R.-H. Baek, M. S. Park, H. C. Sagong, S. H. Sakong, B. H. Lee, G. Bersuker, H. H. Tseng, R. Jammy and Y. H. Jeong, "PBTI and HCI Stress-Induces Trap Generation in SiO2/HfO2 Gate Stack NMOSFETs and its impact on Low Frequency Noise," 5th International Symposium on Advanced Gate Stack Technology (ISAGST 2008), Austin , USA, Sep. 29 - Oct. 1, 2008.
3. K. T. Lee, C. Y. Kang, S. H. Hong, H. S. Choi, G. B. Choi, J. C. Kim, S. H. Song, R.-H. Baek, M. S. Park, H. C. Sagong, S. H. Sakong, S. W. Jung, H. K. Park, H. S. Hwang, B. H. Lee and Y. H. Jeong, "Comparison of PECVD and RTCVD CESL Nitride Stressor in Reliability and Performance Improvement for High-k/Metal Gate CMOSFETs," Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials (SSDM 2008), Tsukuba, Japan, Sep. 23-26, 2008, pp. 362-363.
2. S. H. Hong, G. B. Choi,R.-H. Baek, H. S. Kang, S. W. Jung, and Y. H. Jeong, "RF Characteristics for 70 nm MOSFETs below 77 K," in Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices 2007, Jun. 25-27, 2007, pp. 33-36.
1. R.-H. Baek, H. S. Kang, J. S. Lee, and Y. H. Jeong, "I-V modeling for nanoscale n-MOSFET from liquid-nitrogen temperature to room temperature," in IEEE NMDC(nanotechnology materials and devices conference) 2006, Oct. 22-25, 2006, pp. 316-317.
Domestic Conferences
32. D. Kim, K. Nam, C. Park, H. You, M. Park and R.-H Baek*, " 3차원 낸드 플래시 공정에서 발생하는 기계적 스트레스의 정량 분석을 통한 성능 개선 방법," Summer Annual Conference of IEIE, Jun 28 - Jun 30, 2023.
31. D. Kim, K. Nam, C. Park, G. Yang, J. Jeong, S. Lee, J. Lim, and R.-H. Baek*, "Analysis of Mechanical Stress on Charge Trap Nitride (CTN) for Program Operation in 3D NAND Flash Memory," The 30th Korean Conference on Semiconductors, Feb 13-15, 2023.
30. S. Lee, J. Jeong, J. Park, J. Lee, S. Lee, J. Lim, and R.-H. Baek*, "Novel scheme to form non-uniform oxide in gate-all-around NCFETs for capacitance matching," The 30th Korean Conference on Semiconductors, Feb 13-15, 2023.
29. K. Cho, C. Park, H. Yun, H. Jang, S. Eom, M. Park, and R.-H. Baek*, "Neural Network-based Prediction for Cross-Temperature Induced VT Distribution shift of 3D NAND flash memory," The 30th Korean Conference on Semiconductors, Feb 13-15, 2023.
28. B. Kang, S.-M Ahn, J. Park, J. An, H. You, and R.-H. Baek*, "BCl3/Cl2 plasma etching process of ferroelectric gate stack for device integration," The 30th Korean Conference on Semiconductors, Feb 13-15, 2023.
27. G. Yang, C. Park, K. Nam, M. Park, H. Kang, J. Sim, and R.-H. Baek*, "Improved ISPP Scheme of 3-D NAND Flash for Narrow Threshold Voltage Distribution," The 29th Korean Conference on Semiconductors, Jan 24-26, 2022.
26. J. Park, K.-K. Choi, B. Kang, J. An, and R.-H. Baek*, "PEALD with Post-treatments for Interface Improvement of HfO2-based Metal-Insulator-Semiconductor Structures," The 29th Korean Conference on Semiconductors, Jan 24-26, 2022.
25. S. Lee, J.-S. Yoon, J. Jeong, S. Lee, J. Lee, J. Lim, and R.-H. Baek*, "Sensitivity Analysis of Each Inner Spacer Thickness Variation in Sub 3-nm Node Si Nanosheet FETs," The 29th Korean Conference on Semiconductors, Jan 24-26, 2022.
24. K. Cho, H. Yun, H. Jang, K. Nam, C. Park, J.-S. Yoon, H.-C. Choi, and R.-H. Baek*, "Improving Program Efficiency of 3D NAND Cell Structure Based on Artificial Neural Network," Summer Annual Conference of IEIE, Jun 30 - Jul 2, 2021. (Best paper award)
23. J. Lee, J.-S. Yoon, S. Lee, J. Jeong, and R.-H. Baek*, "Power, Performance and Area Analysis of Source/Drain Patterning n/p FinFETs based 6T-SRAM cell for 3-nm technology node," The 27th Korean Conference on Semiconductors, Feb 12-14, 2020.
22. J. An, K. Choi, B. Kang, and R.-H. Baek*, "Defect curing effects on high-k gate stack (Al/Al2O3/Si-sub) by using H2 plasma treatment and rapid thermal anneal," The 27th Korean Conference on Semiconductors, Feb 12-14, 2020.
21. K. Nam, C. Park, J.-S. Yoon, H. Jang, and R.-H. Baek*, "The Origin of Incremental Step Pulse Programming (ISPP) Slope Degradation in NAND Flash Memory," The 27th Korean Conference on Semiconductors, Feb 12-14, 2020.
20. B. Kang, K. Choi, J. An, and R.-H. Baek*, "Demonstration of TiO2 based ultra high-k (k=30) MIS capacitor and its electrical properties," The 27th Korean Conference on Semiconductors, Feb 12-14, 2020.
19. S. Lee, J.-S. Yoon, J. Jeong, and R.-H. Baek*, “Observation of Mobility and Velocity Behaviors in Ultra Scaled Lg=15 nm Silicon Nanowire pMOSFETs with Different Channel Diameters,” The 26th Korean Conference on Semiconductors, Feb 13-15, 2019.
18. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek*, “Vth Variation Induced by S/D Mole Fraction and Si/SiGe Intermixing of Si-NSFETs,” The 26th Korean Conference on Semiconductors, Feb 13-15, 2019.
17. S. Lee, J.-S. Yoon, J. Jeong, and R.-H. Baek*, “Observation of Mobility and Velocity as Channel Diameter Change in the Shrunk Lg = 18nm Silicon Nanowire MOSFETs,” The Institute of Semiconductor Engineers Conference, Dec. 12. 2018.
16. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek*, “Geometric Optimization of Silicon Gate-All-Around Field-Effect Transistors (GAAFETs) for DC/AC Performances,” The Institute of Semiconductor Engineers Conference, Dec. 12. 2018.
15. H. Jang, C. Park, and R.-H. Baek*, “Design Strategy of 20nm node single PRAM cell based on TCAD Simulation”, The Institute of Semiconductor Engineers Conference, Dec. 12. 2018.
14. I. Park, S. Baek, R.-H. Baek, and J.-S Lee, “Improved Thermal Stability and Lower Sheet Resistance of NiSi with Carbon Pre-silicidation Implant,” The 25th Korean Conference on Semiconductors, Feb. 5-7, 2018.
13. S. Baek, I. Park, R.-H. Baek, J.-S. Lee “Low Frequency Noise in SiC Double-Implant MOSFETs,” The 25th Korean Conference on Semiconductors, Feb. 5-7, 2018.
12. S.-H. Lee, R.-H. Baek, C.-H. Park, M.-D. Ko, K. H. Yeo, D.-W. Kim, Dae M. Kim, and Y.-H. Jeong, "Investigation of GIDL Behavior in Si-Nanowire FET with Hot Carrier Stress,” The 18th Korean Conference on Semiconductors, Feb. 16-18, 2011.
11. R.-H. Baek, C. K. Baek, H.-S. Choi, J. S. Lee, Y. Y. Yeoh, K. H. Yeo, D.-W. Kim, Kinam Kim, Dae M. Kim, and Y. H. Jeong, “Accurate Extraction of Volume Trap Density from Si-Nanowire FET using the Newly Developed Cylindrical Coordinate Based 1/f noise model,” The 17th Korean Conference on Semiconductors, Feb 24~26, 2010, pp. 91-92.
10. S.-H. Lee, R.-H. Baek, C. K. Baek, C.-H. Park, M.-D. Ko, and Y.-H. Jeong, "GIDL Analysis of Underlap Double Gate MOSFET with Variable Channel Thickness and Doping Using Quantum Simulation,” in Proceedings of Semiconductor Society, IEEK Summer Conference 2010, Jun. 16-18, 2010.
9. M.-D. Ko, C.-H. Park, R.-H. Baek, S.-H. Lee, and Y.-H. Jeong, "Comparative Study on Device Performance of Junctionless Double-Gate MOSFET,” in Proceedings of Semiconductor Society, IEEK Summer Conference 2010, Jun. 16-18, 2010.
8. C. H. Park, R.-H. Baek, G. B. Choi, H. S. Choi, H. C. Sagong, K. H. Kim, J. H. Cho, S. H. Sakong, J. S. Lee, and Y. H. Jeong, “Fabrication, DC and Low Frequency Noise Characteristics of Silicon Nanowire FET,” 2009 IEEK FALL CONFERENCE, Nov 28, 2009, pp. 185-186.
7. S. H. Kim, D. Y. Choi, H. C. Sagong, R.-H. Baek, and Y. H. Jeong, "Hot Electron Degradation Effects in 35-nm InAlAs/InGaAs Metamorphic HEMT", 2009 IEEK FALL CONFERENCE, Nov 28, 2009.
6. H. C. Sagong, K. T. Lee, G. B. Choi, H. S. Choi, R.-H. Baek, S. H. Song, M. S. Park, S. H. Lee, S. W. Jung, and Y. H. Jeong, "RF Degradation of Short Channel Metal Gate/High-k Dielectric nMOSFET by Hot Carrier Effect," 2009 IEEK Summer Conference, Jul 8~10, 2009, vol. 32, no. 1, pp. 466.
5. G. B. Choi, S. H. Hong, H. S. Choi, R.-H. Baek, K. T. Lee, M. S. Park, S. H. Song, J. C. Kim, H. C. Sagong, H. D. Lee, and Y. H. Jeong, "Effective Mobility Extraction of the Advanced MOSFETs Using RF Modeling," The 16th Korean Conference on Semiconductors, Feb 18~20, 2009, pp. 206-207.
4. M. S. Park, S. H. Hong, H. S. Choi, G. B. Choi, R.-H. Baek, S. H. Song, K. T. Lee, J. C. Kim, H. C. Sagong, H. D. Lee, and Y. H. Jeong, "DC and Reliability Characteristics of 45 nm Node MOSFETs With Using HfSiON/TiN Gate Stacks," The 16th Korean Conference on Semiconductors, Feb 18~20, 2009, pp. 80-81.
3. H. C. Sagong, K. T. Lee, S. H. Hong, H. S. Choi, G. B. Choi, R.-H. Baek, S. H. Song, M. S. Park, J. C. Kim, C. H. Park, S. W. Jung, C. Y. Kang, and Y. H. Jeong, "RF Characteristics in Metal Gate/high-k Dielectric nMOSFETs at Cryogenic Temperature," The 16th Korean Conference on Semiconductors, Feb 18~20, 2009, pp. 194-195.
2. G. B. Choi, R.-H. Baek, H. S. Kang, and Y. H. Jeong, "70 nm CMOS BSIM4 Macro modeling for RFIC design," in IEEK Summer Conference 2006, Jun. 21-23, 2006, vol. 29, no. 2, pp. 613-614.
1. R.-H. Baek, G. B. Choi, S. H. Hong, H. S. Kang, and Y. H. Jeong, "Optimized scalable I-V Modeling for 70nm Gate Length Nano-CMOS Using BSIM4," in Proceedings of Semiconductor Society, IEEK Summer Conference 2005, Jun. 24, 2005.