BOOK CHAPTERS

4. H.-C Choi, R.-H. Baek, J.-S. Yoon, and H. Yun, “Method for setting of semiconductor manufacturing parameter and computing device for executing the method,” Korean Patent Registration No. 10-2546528, Jun 19th, 2023.

3. R.-H. Baek and J.-S. Yoon, "Chapter 5: Characterization of Silicon FinFETs under nanoscale dimension," in Semiconductor and Technologies for Future Ultra Low Power Electronics, Taylor & Francis, London, United Kingdom: Informa UK Limited. 2021.

2. Y.-H. Jeong, S.-H. Lee, Y.-R. Kim, R.-H. Baek, D.-W. Kim, J.-S. Lee, and Dae M. Kim. (June 17, 2013). Characterization of Gate-All-Around Si-Nanowire Field-Effect Transistor: Extraction of Series Resistance and Capacitance-Voltage Behavior (pp.737-747). In Jame E. Morris and Krzysztof Iniewski, Nanoelectronic Device Applications Handbook, CRC Press.

1. Dae Mann Kim, Bomsoo Kim, Rock-Hyun Baek. (Jan 1, 2014). Silicon Nanowire Field-Effect Transistor (pp.63-88). In D. M. Kim and Y.-H. Jeong, Nanowire Field Effect Transistors: Principles and Applications, Springer New York. DOI 10.1007/978-1-4614-8124-9_4.

PATENTS

36. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, "Method for fabricating a field-effect transistor with size-reduced source/drain epitaxy," US Patent Application No. 11894424, Feb 6th, 2024.

35. R.-H. Baek, H. Yun, CK Kim, S. Han, H. Byeon and M. Yoo, "Method and apparatus for evaluating influence of process on semiconductor device performance and application thereof," Korean Patent Application No. 10-2023-0187638, Dec 20th, 2023.

34. R.-H. Baek and K. Nam, "Memory devices and methods for program disturbance suppression," Korean Patent Application No. 10-2023-0178740, Nov 11th, 2023.

33. R.-H. Baek, K. Cho, H.-C Choi and  J.-S Lee, "Cell-level analysis method of memory based on graph neural network and computing device for performing the same," Korean Patent Application No. 10-2023-0149979, Nov 2nd, 2023.

32. R.-H. Baek, H. Yun, C. An and H.-C Choi, "Learning method for semiconductor process optimization and computing device to perform the same," Korean Patent Application No. 10-2023-0144301, Oct 26th, 2023.

31. R.-H. Baek, J. Lee and J.-S Yoon, "Monolithic three-dimensional semiconductor integrated circuit device and fabrication method thereof," Korean Patent Application No. 10-2587997, Oct 6th, 2023.

30. R.-H. Baek and S. Lee, "Gate-all-around field-effect transistor with extended sorce/drain,"  US Patent Application No. 18367854, Sep 13th, 2023.

29. R.-H. Baek, H. Yun, CK. Kim and H. Byeon, "Method and apparatus for setting semiconductor device manufacturing parameter," US Patent Application No. 18458896, Aug 30th, 2023.

28. R.-H. Baek and K. Nam, "Program Method for Suppressing Program Disturbance in 3D NAND Flash," Korean Patent Application No. 10-2023-0111519, Aug 24th, 2023.

27. R.-H. Baek and S. Lee, "Gate-all-around field-effect transistor with extended source/drain and manufacturing method thereof," Korean Patent Application No. 10-2023-0083347, Jun 28th, 2023.

26. R.-H. Baek, J.-S Yoon, H.-C Choi and H. Yun, "Method for setting of semiconductor manufacturing parameter and computing device for executing the method," Korean Patent Application No. 10-2546528, Jun 19th, 2023.

25. R.-H. Baek, J. Jeong and J.-S Yoon, "Gate-all-around field-effect transistor with tench inner-spacer and manufacturing method thereof," Korean Patent Application No. 10-2543931, Jun 12th, 2023.

24. R.-H. Baek and S. Lee, "Gate-all-around field-effect transistor with extended source/drain and manufacturing method thereof," Korean Patent Application No. 10-2023-0021300, Feb 17th, 2023.

23. R.-H. Baek and J. Jeong, "Gate-all-around field effect transistor having trench inner spacers and METHOD FOR manufacturing SAME," Taiwanese Patent Application No. 112100887, Jan 9th, 2023.

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22. R.-H. Baek and J. Jeong, "Gate-all-around field effect transistor with trench inner spacers and manufacturing method thereof," PCT Patent Application No. PCT/KR2022/021740, Dec 30th, 2022.

21. R.-H. Baek and J. Jeong, "Gate-all-around field effect transistor with trench inner spacers and manufacturing method thereof," Korean Patent Application No. 10-2022-0190897, Dec 30th, 2022.

20. R.-H. Baek, J. Jeong, and J.-S. Yoon, "Gate-all-around field-effect transistor with trench inner-spacer and fabrication method thereof," Taiwanese Patent Application No. 111146434, Dec 2nd, 2022.

19. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, "Method for fabricating a field-effect transistor with size-reduced source/drain epitaxy," US Patent Application No. 18071876, Nov 30th, 2022.

18. R.-H. Baek and H. Yun, "APPARATUS AND METHOD FOR SETTING SEMICONDUCTOR," US Patent Application No. 17983319, Nov 8th, 2022.

17. R.-H. Baek and H. Yun, "Method and apparatus for setting semiconductor device manufacturing parameter," Korean Patent Application No. 10-2022-0116011, Sep 15th, 2022.

16. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor without punch-through stopper and fabrication method thereof,” US Patent Registration No. 11,387,317, Jul 12th, 2022.

15. R.-H. Baek, J. Jeong, and J.-S. Yoon, "Gate-all-around field-effect transistor with trench inner-spacer and fabrication method thereof," PCT Patent Application No. PCT/KR2022/006837, May 12th, 2022.

14. R.-H. Baek, J.-S. Yoon, “Single structure CASCODE device and fabrication method thereof,” Korean Patent Registration No. 10-2394193, Apr 29th, 2022.

13. R.-H. Baek, H. Yun, "APPARATUS AND METHOD FOR SETTING SEMICONDUCTOR," Korean Patent Application No. 10-2022-0025392, Feb 25th, 2022.

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12. H.-C Choi, R.-H. Baek, J.-S. Yoon, and H. Yun, “Method for setting of semiconductor manufacturing parameter and computing device for executing the method,” US Patent Application No. 17551450, Dec 15th, 2021.

11. R.-H. Baek, J. Lee, and J.-S. Yoon, "Monolithic three-dimensional semiconductor integrated circuit device and fabrication method thereof," Korean Patent Application No. 10-2021-0110079, Aug 20th, 2021.

10. R.-H. Baek, J. Jeong, and J.-S. Yoon, "Gate-all-around field-effect transistor with trench inner-spacer and fabrication method thereof," Korean Patent Application No. 10-2021-0108414, Aug 18th, 2021.

9. R.-H. Baek, J.-S. Yoon, "Single structure CASCODE device and method of manufacturing same," US Patent Application No. 17387876, Jul 28th, 2021.

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8. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof,” Korean Patent Registration No. 10-2183131, Nov 19th, 2020.

7. H.-C Choi, R.-H. Baek, J.-S. Yoon, and H. Yun, “Method for setting of semiconductor manufacturing parameter and computing device for executing the method,” Korean Patent Application No. 10-2020-0133780, Oct 15th, 2020.

6. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor without punch-through stopper and fabrication method thereof,” Korean Patent Registration No. 10-2133208, Jul 7th, 2020.

5. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof,” US Patent Application No. 16898706, Jun 11th, 2020.

4. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Metal source/drain-based metal-oxide-semiconductor field-effect transistor and method for fabricating the same,” Korean Patent Registration No. 10-2088706, Mar 9th, 2020.

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3. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “METAL SOURCE/DRAIN-BASED MOSFET AND METHOD FOR FABRICATING THE SAME,” US Patent Application No. 16562693, Sep 6th, 2019.

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2. D.-W. Kim, Dae M. Kim, Y.-H. Jeong, S. Y. Park, C. H. Park, R.-H. Baek, and S.-H. Lee, “Field Effect Transistor and Method of Fabricating the Same,” US Patent Publication No.US20130285019 A1, Oct 31th, 2013.

1. D.-W. Kim, Dae M. Kim, Y.-H. Jeong, S. Y. Park, C. H. Park, R.-H. Baek, and S.-H. Lee, “Field Effect Transistor and Method of Fabricating the Same,” Chinese Patent Publication No.CN103378161 A, Oct 30th, 2013.

Invited talks

7. "Si Gate-All-Around Nanosheet FET: the Key Enabler of 3nm Technology Node", The 28th Korean Conference on Semiconductor (한국반도체학술대회), Jan 25th~29th, 2021.

6. "Performance Knobs on Ultra Scaled Multi-Gate Transistor", SK Hynix, Feb 20th, 2019.

5. "4차 산업혁명에 따른 반도체 기술 개발 방향 및 시장 상황", Yeungnam University, Nov 16th, 2018.

4. "차세대 로직 기술", 반도체디스플레이 심포지움, Oct 26th, 2018.

3. "SiC FET를 포함한 Logic 소자의 분석 및 모델링 기법", KERI(한국전기연구원), Sep 19th, 2018.

2. "Multi-Gate Device Modeling and Reliability Issues", SAMSUNG Electronics, Memory Division, Jun 26th, 2018.

1. "Sub 10nm CMOS Logic Technology for Mobile Era", Yeungnam University, Apr 14th, 2017.