Research Area

We focus on the research about the VLSI / SoC design issues and architecture challenges for intelligent, biomedical, automotive and mobile systems. Our research interests lie primarily in the area of VLSI / SoC / 3D IC design, test methodology, IC reliability and hardware security.

VLSI/SoC/3D IC Design Technology

– Parallel Processing: Biomedical Processor, High-Performance Computing (HPC)
– Artificial Intelligence (AI): AI accelerator, Deep Neural Network
– Reliability: Automotive IC, High-Bandwidth Memory (HBM)

VLSI/SoC/3D IC Testing Technology

– Test Methodology: Reduced Pin Count Test (RPCT), Massive Parallel Test (MPT)
– Scan Test: Compression, Low Power Test, Diagnosis, Test Access Mechanism
– Through Silicon Via (TSV): Test Structure, Test Optimization, TSV Repair

Hardware Security and Robust Design Methodology

– Security and Trust: Detection/Protection Circuits Against Physical Attacks
– Design Methodology: Design-for-Testability(DFT), Design-for-Security(DFS), Design-for-Reliability(DFR)

Memory Test and Repair Methodology

– Memory Test: Built-in Self Test (BIST), 3D-DRAM Control, Built-off Self Test (BOST)
– Memory Repair: Redundancy Analysis (RA), Built-in RA (BIRA), Built-in Self-Repair (BISR)

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