RESEARCH

Research Interests

1. Technology Development

- Give insight of power, performance, area, variability and reliability improvement for next generation technology 

2. Design Enablement

-  Develop path-finding PDK (Layout, LVS, PEX, DRC, Compact Model)

- Develop device-physics & AI based EDA solution

- Design-Technology Co-optimization (DTCO) 

3. Target Devices

- Logic device

- 3D NAND Flash/DRAM device

- Display device

- New Memory device 

- Neuromorphic device

- Organic device

- High Frequency (or Radio Frequency) Power device 

• WHAT’S PATH-FINDING PDK?

PDK is a database that specifies a technology; it contains all the information required to design an IC. “Path-finding PDK“ incorporates data about future technology (device electrical properties, mask info., design rules, types and layout of cells, etc.) where options have not been decided or standardized, path-finding PDK includes various options. The designers can then make their early design studies trying out the available options. In addition, in the latest technologies, the parasitic effects such as parasitic RC delay, IR drop, local strain effect, and self-heating etc. becomes very important and they are strongly dependent on the design layout style. So, the accurate estimation of various technology options can be performed at the circuit level. That’s why we need path-finding PDK.

• WHAT’S DESIGN TECHNOLOGY CO-OPTIMIZATION (DTCO)?

Device engineers and designers have started to discuss exploiting the concept of virtual fabrication in order to hedge the risk arising from difficulties in optimizing many new knobs simultaneously. Concurrent optimization of design and technology based on prediction of semiconductor hardware characteristics has now become an integral component of technology development. Traditional design and technology co-optimization (DTCO) has focused on the interplay between technology (device architecture and integration) and design (design rule and layout scheme) in terms of design for manufacturability. As silicon scaling approaches to fundamental limit, however, the transistor performance is highly susceptible to design rule scaling and the parasitic RC portion of MOL and BEOL has increased. In addition, design impacts of new process knobs should be addressed in systematic manner. Thereby, the interplay between design and device performance has become increasingly important.