Journal Paper
International Journal
[85] C. Ra, et. al., "Analyzing AI hardware architecture design based on logic-in-memory ferroelectric FinFET (Fe-FinFET) at sub-3nm technology nodes," (under review) (Co-corresponding author)
[84] Y. S. Cha, et. al., "Novel Data-Driven Compact Modeling for RRAM Using Deep Neural Networks," (under review) (Co-corresponding author)
[83] Chanwoo Park, et. al., "Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation," (under revision) (Co-corresponding author)
[82] Juhwan Park, Huijun Kim, et. al., "Impacts of Interconnect on Ferroelectic FinFET-based Logic-in-Memory Circuits at 3nm Technology Node," (under review) (Co-corresponding author)
[81] Gunhee Choi, et. al., "Radiation effects on multi-channel forksheet-FET and nanosheet-FET considering the bottom dielectric isolation scheme", (under review) (Corresponding author)
[80] Heonsu Ahn, et. al., "Scalable one-dimensional metal networks by deterministic van der Waals epitaxy," (under review) (Co-author)
[79] Ki Seok Kim, et. al., "Seamless monolithic three-dimensional integration of single-crystalline films by growth," (under revison) (Co-author)
[78] Jongwook Jeon, "Transient Response Modeling Methodology of TFT for OLED Display," (under review) (First/Corresponding author)
[77] Hanggyo Jung, Jeesoo Chang, and Jongwook Jeon, "Evaluation of various phase-transition materials for steep switching super-low power application in the latest CMOS technology node," Results in Physics, Accepted, 2024 (Corresponding author)
[76] Jae Seok Hur, Sungsoo Lee, Jiwon Moon, Hang-Gyo Jung, Jongwook Jeon, Seong Hun Yoon, Jin-Hong Park, and Jae Kyeong Jeong, "Oxide and 2D TMD Semiconductors for 3D DRAM Cell Transistors," Nanoscale Horizons, Accepted, 2024. (Co-author)
[75] Taeho Kang, Joonho Park, Hanggyo Jung, Haeju Choi, Nayeong Lee, Jongwook Jeon, Yong-Hoon Kim, and Sungjoo Lee, "High-κ dielectric (HfO2)/2D semiconductor (HfSe2) gate stack for low-power steep-switching computing devices," Advanced Materials, Accepted, 2024 (Co-author)
[74] Huijun Kim, Juhwan Park, Hanggyo Jung, Jihoon Park, Changho Ra, and Jongwook Jeon, "Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency," npj 2D Materials and Applications, Accepted, 2024. (Co-corresponding author)
[73] Sangki Cho, Sueyeon Kim, Myounggon Kang, Seungjae Baik, and Jongwook Jeon, "Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine Grain Logic-in-Memory Devices," Micromachines, Accepted, 2024 (Corresponding author)
[72] Wookyung Kwon, Changhyun Yoo, and Jongwook Jeon, "Electro-Thermal Modeling of Multi-Nanosheet FETs with Various Layouts", IEEE Trans Electron Devices, Accepted, 2024. (Corresponding author)
[71] Yunjae Kim, Hyoungsoo Kim, Jongwook Jeon, Seungjae Baik, and Myounggon Kang, "Circuit simulation of floating-gate FET (FGFET) for logic application," Memories-Materials, Devices, Circuits and Systems, p. 100090, Oct. 2023. (Co-author)
[70] Moonjeong Choi, Juhwan Park, Seoungyeol Choi, Kyungbae Kwon, Yeji Lee, Wonyeong Jang, and Jongwook Jeon, "Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Node," Journal of Semiconductor Technology and Science, vol. 23, no. 4, pp. 215-227, Aug. 2023. (Corresponding author)
[69] Sueyeon Kim, Sangki Cho, Insoo Choi, Myounggon Kang, Seungjae Baik, and Jongwook Jeon, "Investigation on Floating Gate Field Effect Transistor (FGFET) for Logic-in-Memory Application," Journal of Physics D: Applied Physics, vol. 56, no. 49, p. 495105, Sept. 2023. (Corresponding author)
[68] Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, and Jongwook Jeon, "Analysis of Logic-in-Memory Full Adder Circuit with Floating Gate Field Effect Transistor (FGFET)," IEEE ACCESS, Sept. 2023 (Corresponding author)
[67] Jae Won Lim, Chang Hyun Yoo, Kiron Park, and Jongwook Jeon, "Self-heating and Electric Field Crowding Effects on Time Dependent Dielectric Breakdown (TDDB) of Stacked Multi-Nanosheet FETs," IEEE ACCESS, July 2023. (Corresponding author)
[66] Seyoung Kim, Seungho Yang, Hyein Lim, Hyein Lee, Jongwook Jeon, Jung Yun Choi, and Jaeha Kim, "An Accurate Layout-Dependent Effect Model In A 10-nm Class DRAM Process Using Area-Efficient Array Test Circuits" IEEE ACCESS, July 2023. (Co-author)
[65] Song Xuyao, Sang Beom Kim, Hanggyo Jung, Jaekyum Kim, Jaewan Mo, Yong Jin Jeong, Jaeyoung Jang, Tae Kyu An, Yun-Hi Kim, and Jongwook Jeon, "Well‐Balanced Ambipolar Charge Transport of Diketopyrrolepyrrole-based Copolymers: Organic Field-Effect Transistors and High-Voltage Logic Applications," Macromolecular Rapid Communications, p.2300271, July 2023. (Corresponding author)
[64] Tien Dat Ngo, Tuyen Huynh, Hanggyo Jung, Fida Ali, Jongwook Jeon, Min Sup Choi, and Won Jong Yoo, "Modulation of Contact Resistance of Dual-Gated MoS2 FETs Using Fermi-Level Pinning-Free Antimony Semi-Metal Contacts," Advanced Science, 2301400, May 2023. (Co-author)
[63] Jihun Park, Hanggyo Jung, Wookyung Kwon, Gunhee Choi, Jeesoo Chang, and Jongwook Jeon, "An investigation of optimal architecture of MoS2 channel field effect transistor on sub-2nm process node," ACS Applied Electronic Materials, 5(4), pp.2239-2248, Apr. 2023. (Corresponding author)
[62] Sangki Cho, Sueyeon Kim, Insoo Choi, Myounggon Kang, Seungjae Baik, and Jongwook Jeon, "Non-volatile Logic-in-Memory Ternary Content Addressable Memory Circuit with Floating Gate Field Effect Transistor," AIP Advances, 13(4), 045211, Apr. 2023. (Corresponding author)
[61] Hanggyo Jung, Jeesoo Chang, Changhyun Yoo, Jooyoung Oh, Sumin Choi, and Jongwook Jeon, "Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3nm Technology Node," Nanomaterials, 12(22), 4096, Nov. 2022. (Corresponding author)
[60] Haeju Choi, Jinshu Li, Taeho Kang, Chanwoo Kang, Hyeonje Son, Jongwook Jeon, Euyheon Hwang, and Sungjoo Lee, “A steep switching WSe2 impact ionization field-effect transistor,” Nature Communications, 13, 6076, Oct. 2022. (Co-author)
[59] Yeji Lee, Wonyeong Jang, Kyungbae Kwon, Jihun Park, Changhyun Yoo, Jeesoo Chang, and Jongwook Jeon, "Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit," IEEE ACCESS, vol. 10, pp.80695-80702, Aug. 2022. (Corresponding author)
[58] Jihun Park, Changho Ra, Jaewon Lim, and Jongwook Jeon, "Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node," Nanomaterials, vol. 12, no. 13, July 2022. (Corresponding author)
[57] Changhyun Yoo, Jeesoo Chang, Yoongeun Seon, Hyunwoo Kim, and Jongwook Jeon, "Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options," IEEE Trans Electron Devices, vol. 69, pp.1524-1531, Mar. 2022. (Corresponding author)
[56] Changhyun Yoo, Jeesoo Chang, Sugil Park, Hyungyeong Kim, and Jongwook Jeon, "Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage," Nanomaterials, vol. 12, no. 4, Feb. 2022. (Corresponding author)
[55] Yeji Kim, Yoongeun Seon, Soowon Kim, Jongmin Kim, Saemin Bae, Inkyung Yang, Changhyun Yoo, Junghoon Ham, Jungmin Hong, and Jongwook Jeon, "Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance," Electronics, vol. 10, no. 10, p.1177, May 2021. (Corresponding-author)
[54] Yoongeun Seon, Jeesoo Chang, Changhyun Yoo, and Jongwook Jeon, "Device and circuit exploration of multi-nanosheet transistor for sub-3 nm technology node," Electronics, vol. 10, no. 2, p.180, Jan. 2021. (Corresponding-author)
[53] Quan Nguyen-Gia, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, "Models of threshold voltage and subthreshold slope for macaroni channel MOSFET," IEEE Electron Device Letters, vol. 41, no. 7, pp. 973-976, May 2020. (Co-author)
[52] Hyunsuk Kim, Dokyun Son, Ilho Myeong, Jaeyeol Park, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, "Optimization of stacked nanoplate FET for 3-nm node," IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1537-1541, Mar. 2020. (Co-author)
[51] Kiron Park, Sujin Im, Keonho Park, Kwonjoo Son, SeungEui Hong, and Jongwook Jeon, “Reliability Analysis Framework for Time Dependent Dielectric Breakdown,” Journal of Semiconductor Technology and Science, vol. 20, no. 1, pp.19-28, Feb. 2020. (Corresponding-author)
[50] Jungmin Hong, Jaewoong Park, Jeawon Lee, Jeonghun Ham, Kiron Park, and Jongwook Jeon, "Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node," Micromachines, vol. 10, no. 12, p.847, Dec. 2019. (Corresponding author)
[49] Kyunghun Kim, Se Hyun Kim, Hyungjin Cheon, Xiaowu Tang, Jeong Hyun Oh, Heesauk Jhon, Jongwook Jeon*, Yun-Hi Kim*, and Tae Kyu An*, "Electrohydrodynamic-Jet (EHD)-Printed Diketopyrrolopyroole-Based Copolymer for OFETs and Circuit Applications," Polymers, vol. 11, no. 11, p.1759, Oct. 2019. (Corresponding author)
[48] Quan Nguyen-Gia, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, "Characteristic length of macaroni channel MOSFET," IEEE Electron Device Letters, vol. 40, no. 11, pp.1720-1723, Sept. 2019. (Co-author)
[47] Yoongeun Seon, Jongmin Kim, Soowon Kim, and Jongwook Jeon, "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel," Electronics, vol. 8, no. 9, p.988, Aug. 2019. (Corresponding author)
[46] Kiron Park, Keonho Park, Sujin Im, SeungEui Hong, Kwonjoo Son, and Jongwook Jeon, "Development of an Advanced TDDB Analysis Model for Temperature Dependency," Electronics, vol. 8, no. 9, p.942, Aug. 2019. (Corresponding author)
[45] Changbeom Woo, Jang Kyu Lee, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Effect of Various Geometry Parameters on the Performance of Nanoplate Field Effect Transistor with Negative Capacitance,” Journal of Nanoscience and Nanotechnology, vol. 19, no. 10, pp. 6736-6740, Oct. 2019. (Co-author)
[44] Jang Kyu Lee, Changbeom Woo, Jongsu Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Analysis of Variation and Ferroelectric Layer Thickness on Negative Capacitance Nanowire Field-Effect Transistor,” Journal of Nanoscience and Nanotechnology, vol. 19, no. 10, pp. 6710-6714, Oct. 2019. (Co-author)
[43] Juhyun Kim, Myunggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node,” Journal of Nanoscience and Nanotechnology, vol. 19, no. 10, pp. 6771-6775, Oct. 2019. (Co-author)
[42] Kyul Ko, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Variability-Aware Simulation Strategy for Gate-All-Around Vertical Field Effect Transistor,” Journal of Nanoscience and Nanotechnology, vol. 19, no. 10, pp. 6715-6721, Oct. 2019. (Co-author)
[41] Hyunsuk Kim, Dokyun Son, Ilho Myeong, Donghyun Ryu, Jaeyeol Park, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET,” IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 2898-2903, July 2019. (Co-author)
[40] Donghyun Ryu, Ilho Myeong, Jang Kyu Lee, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device,” IEEE Transactions on Electron Devices, vol. 66, no. 6, pp. 2532-2537, June 2019. (Co-author)
[39] Hyungwoo Ko, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Modeling of Nanoplate Parasitic Extension Resistance and Its Associated Dependency on Spacer Materials,” IEEE Transactions on Electron Devices, vol. 66, no.6, pp. 2527-2531, June 2019. (Co-author)
[38] Jongsu Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Fringe Capacitance Modeling in NanoPlate MOSFET Using Conformal Mapping,” IEEE Transactions on Electron Devices, pp. 1-4, Mar. 2019. (Co-author)
[37] Ko Kyul, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Compact Model Strategy of Metal-Gate Work-Function Variation for Ultrascaled FinFET and Vertical GAA FETs,” IEEE Transactions on Electron Devices, pp. 1-4, Jan. 2019. (Co-author)
[36] Youngsoo Seo, Myounggon Kang, Jongwook Jeon*, and Hyungcheol Shin*, “Prediction of Alpha Particle Effect on 5-nm Vertical Field-Effect Transistors ,” IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 806-809, Jan. 2019. (Corresponding author)
[35] Ilho Myeong, Dokyun Son, Hyunsuk Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing IOFF in Various Sub-10-nm 3-D Transistors,” IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 647-654, Jan. 2019. (Co-author)
[34] Hyungwoo Ko, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, "Device Investigation of Nanoplate Transistor With Spacer Materials,“ IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 766-770, Jan. 2019. (Co-author)
[33] Hyunsuk Kim, Dokyun Son, Ilho Myeong, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, ”Analysis on Self-Heating Effects in Three-Stacked Nanoplate FET,” IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4520-4526, Oct. 2018 (Co-author)
[32] Dokyun Son, Ilho Myeong, Hyunsuk Kim, Myounggon Kang, Jongwook Jeon*, and Hyungcheol Shin*, “Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs,” IEEE Transactions on Electron Devices, vol.65, no.7, pp.00, June 2018. (First author)
[31] Jongwook Jeon, Heesauk Jhon, Myounggon Kang, Ho Jun Song, and Tae Kyu An, “Quinacridone-quinoxaline-based copolymer for organic field-effect transistors and its high-voltage logic circuit operations,” Organic Electronics, vol. 56, pp. 1-4, May. 2018. (First author)
[30] Kyunghun Kim†, Jongwook Jeon†, Yeon Hee Ha, Hyojung Cha, Chan Eon Park, Myunggon Kang, Heesauk Jhon, Soon-Ki Kwon, Yun-Hi Kim, and Tae Kyu An, “Ambipolar charge transport of diketopyrrolepyrrole-silole-based copolymers and effect of side chain engineering: Compact model parameter extraction strategy for high-voltage logic applications,” Organic Electronics, vol. 54, pp. 1-8, Mar. 2018. (First author)
[29] Jongwook Jeon, Hee-Sauk Jhon, and Myunggon Kang, “Circuit modeling of the electro-thermal behavior of nanoscale bulk-FinFETs,” Journal of Computational Electronics, Vol. 17, Issue 1, pp. 146-152, Mar.2018. (First author)
[28] Jongwook Jeon, Hee-Sauk Jhon, and Myunggon Kang, “Investigation of electro-thermal behaviors of 5 nm bulk FinFET,” IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 5284-5287, Dec. 2017. (First author)
[27] Hee-Sauk Jhon, Jongwook Jeon*, and Myunggon Kang*, “Design optimization of RF low noise amplifier in twin-well CMOS process,” Microwave and Optical Technology Letters, vol. 59, No.12, pp.3151-3154, Dec., 2017. (Corresponding author)
[26] Hee-Sauk Jhon, Jongwook Jeon*, and Myunggon Kang*, “Noise figure improvement by controlling wiring effects in RF low noise amplifiers,” Microwave and Optical Technology Letters, vol. 59, No.6, pp.1405-1407, June 1, 2017. (Corresponding author)
[25] Yong Jin Jeong†, Jongwook Jeon†, Sangkug Lee, Myounggon Kang, Heesauk Jhon, Ho Jun Song, Chan Eon Park, and Tae Kyu An, “Development of organic semiconductors based on quinacridone derivatives for organic field-effect transistors: high-voltage logic circuit applications,” IEEE Journal of the Electron Device Society, Vol.5, No. 3, pp. 209-213, May 1, 2017. (First author)
[24] Kyunghun Kim, Jinhwi Cho, Heesauk Jhon, Jongwook Jeon, Myounggon Kang, Chan Eon Park, Jihoon Lee and Tae Kyu An, “Repurposing compact discs as master molds to fabricate high-performance organic nanowire field-effect transistors,” Nanotechnology, Vol.28, p. 205304, Apr 26, 2017. (Co-author)
[23] Hee-Sauk Jhon, Jongwook Jeon*, and Myunggon Kang*, “Extremely low power LNA biased with 0.25-V drain-to-source voltage for 3-to-5 GHz UWB-IR application,” Microelectronics Journal, vol. 61, pp.1-5, Jan. 1, 2017. (Corresponding author)
[22] Hee-Sauk Jhon, Jongwook Jeon, Myunggon Kang, and Woo Young Choi, “A sub-0.5V operating RF low noise amplifier using tunneling-FET,” Japanese Journal of Applied Physics, vol. 56, p. 020303, Jan. 6, 2017. (Co-author)
[21] Jongwook Jeon and Myunggon Kang, “Circuit level layout optimization of MOS transistor for RF and noise performance improvements”, IEEE Transactions on Electron Devices, Vol. 63, No.12, pp. 4674-4677,Oct 11. 2016. (First author)
[20] Jongwook Jeon, Ik-Joon Chang, and Myunggon Kang, “Accurate estimation technique of low frequency noise in NAND flash cell array,” IEEE Electron Device Letters, Vol. 37, No.6, pp. 724-727, Apr12. 2016. (First author)
[19] Jongwook Jeon, Yoon Kim, and Myunggon Kang, “Investigation of the induced gate noise of nanoscale MOSFETs in the very high frequency region,” Semiconductor Science and Technology, vol. 31, p. 065004, Apr14. 2016. (First author)
[18] Jongwook Jeon and Myunggon Kang, “Shot noise effect on noise source and noise parameter of 10-nm-scale quasi-ballistic n-/p-type MOS devices,” Japanese Journal of Applied Physics, vol. 55, p. 054102, Apr15. 2016. (First author)
[17] Donggwan Shin, Changwook Jeong, Jongwook Jeon, and Ilsub Chung, “Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating,” IEEE Electron Device Letters, Vol. 35, No.12, pp. 1191-1193, Oct28. 2014. (Co-author)
[16] Jongwook Jeon, Il Han Park, Myounggon Kang, Wookghee Hahn, Kihwan Choi, Sunghee Yun, Gi-Young Yang, Keun-Ho Lee, Young-Kwan Park, and hilhee Chung, “Accurate Compact Modeling for Sub-20nm NAND Flash Cell Array Simulation Using PSP Model,” IEEE Transactions on Electron Devices, Vol. 59, No.12, pp. 3503-3509, Dec. 2012. (First author)
[15] Jaehong Lee, Jongwook Jeon, Junsoo Kim, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, "Experimental investigation of quasi-ballistic carrier transport characteristics in 10-nm scale MOSFETs," IEEE Transactions on Nanotechnology, Vol. 10, No. 5, pp. 975-979, Sep. 2011. (Co-author)
[14] Jongwook Jeon, Byung-Gook Park, and Hyungcheol Shin, “Investigation of thermal noise factor in nanoscale MOSFETs,” Journal of Semiconductor Technology and Science, vol.10, no.3, pp. 213-218, Sep. 2010. (First author)
[13] Bong Chan Kim, Jongwook Jeon, and Hyungcheol Shin, "Temporal noise analysis and reduction method in CMOS image sensor readout circuit", IEEE Transactions on Electron Devices, Vol. 56 No. 11 pp.2489-2495, Nov. 2009. (Co-author)
[12] Jae Ho Lee, Jaehong Lee, Jongwook Jeon, Hee-Sauk Jhon, and Hyungcheol Shin, "Deembedding accuracy for device scale and interconnection line parasitics", IEEE Microwave and Wireless Components Letters, Vol. 19 No. 11 pp.713-715, Nov. 2009. (Co-author)
[11] Jongwook Jeon, Ickhyun Song, Jong Duk Lee, Byung-Gook Park, and Hyungcheol Shin, “Application of the compact channel thermal noise model of short channel MOSFETs to CMOS RFIC Design,” Institute of Electronics, Information and Communication Engineers(IEICE) Transactions on Electronics, vol. E92-C, no. 5, pp. 627-634, May 2009. (First author)
[10] Yeonam Yun, Hee-Sauk Jhon, Jongwook Jeon, Jaehong Lee, and Hyungcheol Shin, “Small-signal modeling of MOSFET cascade with merged diffusion,” Solid-State Electronics, vol. 53, no. 5, pp. 520-525, May 2009. (Co-author)
[9] Jongwook Jeon, Jaehong Lee, Chan Hyeong Park, Hyunwoo Lee, Hansu Oh, Ho-Kyu Kang, Byung-Gook Park, and Hyungcheol Shin, “Accurate extraction of excess channel thermal noise coefficient in Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model 4,” Japanese Journal of Applied Physics, vol. 48, no. 4, p. 04C037, Apr. 2009. (First author)
[8] Hee-Sauk Jhon, Ickhyun Song, Jongwook Jeon, MinSuk Koo, Byung-Gook Park, and Jong Duk Lee, and Hyungcheol Shing, “Low power size-efficient CMOS UWB low-noise amplifier design,” Microwave and Optical Tech. Letters, vol. 51, no. 2, pp. 494-496, Feb. 2009. (Co-author)
[7] Ickhyun Song, Jongwook Jeon, Hee-Sauk Jhon, Junsoo Kim, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shing, “A simple figure of merit of RF MOSFET for low-noise amplifier design,” IEEE Electron Device Letters, vol. 29, no. 12, pp. 1380-1382, Dec. 2008. (Co-author)
[6] H.-S. Jhon, I. Song, J. Jeon, H. Jung, M. Koo, B.-G. Park, and H. Shin, ” 8mW 17/24 GHz dual-band CMOS low-noise amplifier for ISM-band application,” Electronics Letters, vol. 44, no. 23, Nov. 2008. (Co-author)
[5] Jongwook Jeon, Yeonam Yun, Junsoo Kim, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, “On the characterization and spatial dependence of channel thermal noise in nanoscale Metal-Oxide-Semiconductor Field Effect Transistors,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2636 – 2640, Apr. 2008. (First author)
[4] Hochul Lee, Youngchang Yoon, Jongwook Jeon, and Hyungcheol Shin, “Analysis of random telegraph signal noise in dual and single oxide device and its application to complementary metal oxide semiconductor image sensor readout circuit,” Japanese Journal of Applied Physics, pp. 2602-2605, Apr. 2008. (Co-author)
[3] Jongwook Jeon, Jong Duk Lee, Byung-Gook Park, and Hyungcheol Shin, “An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects,” Solid-State Electronics, pp. 1034-1038, July 2007. (First author)
[2] Jongwook Jeon, Jong Duk Lee, Byung-Gook Park, and Hyungcheol Shin, “Analytical noise parameter model of short-channel RF MOSFETs,” Journal of Semiconductor Technology and Science, pp. 88-93, June 2007. (First author)
[1] Hyungcheol Shin, Seyoung Kim, and Jongwook Jeon, “Analytical thermal noise model of deep-submicron MOSFETs,” Journal of Semiconductor Technology and Science, pp. 206-209, Sept. 2006. (Co-author)
Domestic Journal
[3] 유창현, 김현우, 선윤근, 강명곤, 전종욱, “3nm급 Multi-Nanosheet Field Effect Transistor의 Bottom Oxide 및 Package에 따른 Self-Heating 변화,” 전자공학회논문지, vol. 58, no. 4, pp. 289-297, Apr. 2021. (Corresponding author)
[2] 김현우, 전종욱, 강명곤, 신형철, “3 nm Node Nanoplate-FET에서 Self-heating Effect의 완화 방법,” 전자공학회논문지, vol. 57, no. 2, pp. 21-26, Feb. 2020. (Co-author)
[1] 유예지, 전종욱, 강명곤, 신형철, “3D TCAD를 이용한 3-㎚ node 나노 플레이트 소자에서의 OFF-State Stress 분석,” 전자공학회논문지, vol. 56, no. 10, pp. 19-24, Oct. 2019. (Co-author)