Conference Paper

International Conference

[XX] ......Updates are needed on the published international conference papers published in 2024-2025......

[34] Chanwoo Park, Hong Chul Nam, Jihun Park, Jongwook Jeon, "FlowSim: An Invertible Generative Network for Efficient Statistical Analysis under Process Variations," 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 157-160, Sept. 2023 (Corresponding author).

[33] Chanwoo Park, Jongwook Jeon, and Hyunbo Cho, "DAT: Leveraging Device-Specific Noise for Efficient and Robust AI Training in ReRAM-based Systems," 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 289-292, Sept. 2023. (Co-author)

[32] Gihong Kim, Changho Ra, Myounggon Kang, and Jongwook Jeon, “Compact Modeling of Ferroelectric Field Effect Transistor (FeFET) for Logic-in-Memory Application,” IEEE International Conference on Electronics, Information, and Communications (ICEIC), Jan., 2021. (First author)

[31] Ilho Myeong, Jongwook Jeon, Myounggon Kang, Hyungcheol Shin, “Analysis of self heating effect in vertical-channel field effect transistor,” 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp.1-5, Mar. 2019. (Co-author)

[30] Juhyun Kim, Ilho Myeong, Minsoo Kim, Sungbak Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Modeling of Channel Current in Sub-threshold Region for Poly-Si based Macaroni Structure in 3D NAND Flash Memories,” 2019 Electron Devices Technology and Manufacturing Conference (EDTM), pp.200-202, Mar. 2019. (Co-author)

[29] Kyul Ko, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Compact model strategy of metal-gate work-function variation for ultrascaled FinFET and vertical GAA FETs,” 2019 Electron Devices Technology and Manufacturing Conference (EDTM), pp.1613-1616, Mar. 2019. (Co-author)

[28] Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Dongiun Lee, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Modeling of lateral migration mechanism during the retention operation in 3D NAND flash memories,” 2019 Electron Devices Technology and Manufacturing Conference (EDTM), pp.261-263, Mar. 2019. (Co-author)

[27] Minsoo Kim, Ilho Myeong, Juhyun Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “BSIM-CMG modeling for 3D NAND cell with macaroni channel,” 2019 Electron Devices Technology and Manufacturing Conference (EDTM), pp.288-290, Mar. 2019. (Co-author)

[26] Jongwook Jeon, Heesauk Jhon, Yoon Kim, and Myounggon Kang, “Accurate Self-heating Simulation for Integrated Circuit Design,” IEEE International Conference on Electronics, Information, and Communications (ICEIC), Jan., 2019 (First author)

[25] Youngseok Jeong, Gwanho Lee, Jongwook Jeon, Hee-Sauk Jhon, Yoon Kim, and Myounggon Kang, “Analysis of natural local self-boosting effect due to down-coupling phenomenon in 3D NAND flash memory,” International Conference on Solid State Devices and Materials, PS-2-19, Sept. 2018. (Co-author)

[24] Jongwook Jeon, “Poly-channel gate-all-around compact model for vertical NAND flash memory array simulation”, Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 47, July 2018. (First author)

[23] Youngsoo Seo, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Analysis of Radiation Effect for Nanoplate Field Effect Transistor,” IEEE Silicon Nanoelectronics Workshop (SNW), June, 2018. (Co-author)

[22] Changbeom Woo, Jang Kyu Lee, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Impact of different parameters in negative capacitance FinFET,” IEEE Silicon Nanoelectronics Workshop (SNW), June, 2018. (Co-author)

[21] Kwanho Lee, Yoon Kim, Jongwook Jeon, and Myounggon Kang, “Analysis of NLSB Effect depending on Cell Pattern and Bias Conditions in 3D NAND Flash Memory,” IEEE International Conference on Electronics, Information, and Communications (ICEIC), Jan., 2018. (Co-author)

[20] Young-Seok Song, Chun-Yee Chu, Jongwook Jeon, Ui-Hui Kwon, Keun-Ho Lee, and SoYoung Kim, “Accurate BEOL statistical modeling methodology with circuit-level multi-layer process variations,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 265-268, Oct. 2017. (Co-author)

[19] Nuo Xu, Jing Wang, Yexin Deng, Yang Lu, Bo Fu, Woosung Choi, Udit Monga, Jongwook Jeon, Jongchol Kim, Keun-Ho Lee, Eun Seung Jung, “Multi-domain compact modeling for GeSbTe-based memory and selector devices and simulation for large-scale 3-D cross-point memory arrays”, IEEE International Electron Devices Meeting(IEDM), Dec. 2016. (Co-author)

[18] Dong-il Bae, Geumjong Bae, Krishna K Bhuwalka, Seung-Hun Lee, Myung-Geun Song, Taek-soo Jeon, Cheol Kim, Wookje Kim, Jaeyoung Park, Sunjung Kim, Uihui Kwon, Jongwook Jeon, Kab-Jin Nam, Sangwoo Lee, Sean Lian, Kang-ill Seo, Sun-Ghil Lee, Jae Hoo Park, Yeon-Cheol Heo, Mark S. Rodder, Jorge A. Kittl, Yihwan Kim, Kihyun Hwang, Dong-Won Kim, Mong-song Liang and ES Jung, “A novel tensile Si (n) and compressive SiGe (p) dual-channelCMOS FinFET co-integration scheme for 5nm logic applications and beyond”, IEEE International Electron Devices Meeting(IEDM), Dec. 2016. (Co-author)

[17] Udit Monga, Jaehee Choi, Jongwook Jeon, Uihui Kwon, Keun-Ho Lee, Seungjin Choo, Taiki Uemura, Soonyoung Lee, Sangwoo Pae, “Charge-collection modeling for SER simulation in FinFETs,” Int. Conf. on Simulation and Semiconductor Processes and Devices(SISPAD), Oct. 2016. (Co-author)

[16] Hyewon Shim, Yoohwan Kim, Jongwook Jeon, Yongsang Cho, Jongwoo Park, Sangwoo Pae, and Haebum Lee, “Mismatch circuit aging modeling and simulations for robust product design and pre-/post-silicon verification,” IEEE Reliability Physics Symposium(IRPS), Apr. 2016. (Co-author)

[15] Yo-Han Kim, Jongwook Jeon, Yong-Un Jang, Yong-Hee Park, Gi-Young Yang, Young-Kwan Park, Moon-Hyun Yoo, and Chil-Hee Chung, “Compact process and layout aware model for variability optimization of circuit in nanoscale CMOS,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 141-144, Oct. 2010. (Co-author)

[14] J. Jeon, J. Lee, J. Kim, C. H. Park, H. Lee, H. Oh, H.-K. Kang, B.-G. Park, and H. Shin, “The first observation of shot noise characteristics in 10-nm scale MOSFETs,” Symposium on VLSI Technology, pp. 48-49, June 2009. (First author)

[13] Hyungcheol Shin, Seungwon Yang, Jongwook Jeon, and Daewoon Kang, “Noise in nano-scale MOSFETs and flash cells,” The 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp. 88-91, Oct. 2009. (Co-author)

[12] Jaehong Lee, Jongwook Jeon, Junsoo Kim, Byung-Gook Park, and Hyungcheol Shin, “Prediction of channel thermal noise in twin silicon Nanowire MOSFET (TSNWFET),” The 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp. 61-63, Oct. 2008. (Co-author)

[11] Jongwook Jeon, Jaehong Lee, Chan Hyeong Park, Jong Shik Yoon, Hyunwoo Lee, Hansu Oh, Byung-Gook Park, and Hyungcheol Shin, “Accurate channel thermal noise modeling in BSIM4,” International Conference on Solid State Devices and Materials, pp. 890-891, Sept. 2008. (First author)

[10] Bong Chan Kim, Jongwook Jeon, and Hyungcheol Shin, “Temporal noise analysis and its reduction method in CMOS imager readout circuit,” International Conference on Solid State Devices and Materials, pp. 278-279, Oct. 2008. (Co-author)

[9] Jongwook Jeon, Ickhyun Song, and Hyungcheol Shin, “Implementation of Channel Thermal Noise Model in CMOS RFIC Design,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 239-242, July 2008. (First author)

[8] Jongwook Jeon, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, “White Noise Characteristics of Nanoscale MOSFETs in All Operating Regions,” Silicon Nanoelectronics Workshop, June 2008. (First author)

[7] Jongwook Jeon, Yeonam Yun, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, “Spatial distrubution of channel thermal noise in short-channel MOSFETs,” International Conference on Solid State Devices and Materials, pp. 448-449, Sept. 2007. (First author)

[6] Hochul Lee, Youngchang Yoon, Jongwook Jeon, and Hyungcheol Shin, “Analysis of random telegraph signal noise in dual and single oxide device and its application to CMOS image sensor readout circuit,” International Conference on Solid State Devices and Materials, pp. 898-899, Sept, 2007. (Co-author)

[5] Jongwook Jeon, Ickhyun Song, In Man Kang, Yeonam Yun, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, “A new noise parameter model of short-channel MOSFETs,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 639-642, June 2007. (First author)

[4] Hochul Lee, Youngchang Yoon, Jongwook Jeon, and Hyungcheol Shin, “Drain voltage dependency of random telegraph signal noise in nano scale MOSFETs,” Silicon Nanoelectronics Workshop, pp. 43-44, June 2007. (Co-author)

[3] Jongwook Jeon, Yujo Yun, Y.W. Kim, and Hyungcheol Shin, “A new analytical model for channel thermal noise of deep-submicron RF MOSFETs,” International SoC Design Conference, pp. 409-410, Oct. 2006. (First author)

[2] Hyungcheol Shin, In Man Kang, Jongwook Jeon, and Joonho Gil, “Active and passive RF device compact modeling in CMOS technologies,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 17-22, Oct. 2006. (Co-author)

[1] Jongwook Jeon, Seyoung Kim, In Man Kang, Kwangsuk Han, and Hyungcheol Shin, “Analytical Thermal Noise Model Suitable for Circuit Design Using Short-Channel MOSFETs”, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 637-640, June 2005. (First author) 

Domestic Conference

[XX] ......Updates are needed on the published domestic conference papers published in 2023-2025......

[67] 박지훈, 전종욱, “Sub-2nm에서 Double Gate 구조를 가지는 2차원 TMDC 채널 특성 평가,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[66] 권경배, 유창현, 전종욱, “3nm mNS-FET의 Bottom Isolation에 따른 RF 특성 및 모델링,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[65] 임재원, 유창현, 전종욱, “나노스케일 Gate-All-Around 소자의 Electric-Field Crowding 특성에 따른 TDDB 특성 분석,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[64] 정항교, 유창현, 송주영, 최수민, 전종욱, “3nm급 HyperFET의 온도에 따른 회로 특성 분석,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[63] 김수연, 강명곤, 백승재, 전종욱, “Floating Gate 기반 Logic-in-Memory 소자 최적화,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[62] 박주환, 김희준, 김승겸, 전종욱, “2차원 TMDC 채널 FeFET 기반 TCAM 회로 특성 분석,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[61] 권우경, 유창현, 전종욱, “3nm mNS-FET의 Self-heating 묘사를 위한 Electro-Thermal SPICE Modeling,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[60] 조상기, 최인수, 김수연, 강명곤, 백승재, 전종욱, “Floating Gate 기반 Logic-in-Memory 소자 Compact Modeling,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[59] 김희준, 박주환, 김승겸, 라창호, 전종욱, “2차원 TMDC 채널 FeFET 기반 Full Adder 회로 특성 분석,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[58] 김승겸, 박주환, 김희준, 라창호, 전종욱, “Multi-level FeFET 위한 Compact Modeling,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[57] 박세훈, 최문정, 최승열, 이예지, 장원영, 권경배, 전종욱, “3nm mNS-FET의 All-Carbon 기반 Interconnect Scheme 회로 특성 분석,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[56] 최수민, 송주영, 정항교, 전종욱, “3nm급 HyperFET 기반 SRAM 특성 분석,” 대한전자공학회 하계 학술대회, June 2022. (Corresponding author)

[55] 최정훈, 문예향, 김재엽, 유이경, 박기찬, 전종욱, “OLED 디스플레이의 내부보상 화소회로 과도응답 모델링 기법,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[54] Hanggyo Jung, Yeji Lee, Jooyoung Oh, Changhyun Yoo and Jongwook Jeon, “A Study on the Optimization Methodology of Steep-Switching Phase-FET and Its Application to 3nm Gate-All-Around Field Effect Transistor,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[53] Wonyeong Jang, Yeji Lee, Kyung-bae Kwon, and Jongwook Jeon, “Circuit Analysis of 3nm GAA mNS-FET Considering Interconnect RC,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[52] Changhyun Im, Sueyeon Kim, Myounggon Kang, Seung Jae Baik, and Jongwook Jeon, “수직 적층형 로직-인-메모리 소자 기반 전가산기 설계,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[51] Jae Won Lim, Chang hyun Yoo, and Jongwook Jeon, “The Effect of Self-heating Effect on the Lifetime of the Time-Dependant Dielectric Breakdown,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[50] Yeji Lee, Hang-gyo Jung, Jooyong Oh, and Jongwook Jeon, “The effect of ptm transition delay time on hyperfet based circuit characteristics,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[49] Chnaghyun Yoo and Jongwook Jeon, “Analysis of self-heating effect considering circuit operation and reliability,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[48] 오주영, 정항교, 이예지, 전종욱, “주변 온도에 따른 상전이 소자 특성 묘사 모델링,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[47] Haesu An, Hyeonjung Shim, Changhyeon Yoo, and Jongwook Jeon, “Alpha Particle Effect according to the presence or absence of Bottom Oxide in 3 nm process Multi-Nanosheet Field Effect Transistor,” The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[46] Jihun Park, Minsung Kim, and Jongwook Jeon, "The Future of Mono-layer MoS2 Channel Transistor without Stacking," The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[45] Sugil Park, Changho Ra, Gihong Kim, Hyungyeong Kim, Changhyun Yoo, and Jongwook Jeon, "3nm Multi-Nanosheet FET-based Ferroelectric FET device Full Adder Characteristics Analysis," The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[44] Hyungyeong Kim, Sugil Park, Gihong Kim, Changho Ra, and Jongwook Jeon, "Characteristic of TCAM based on Ferroelectric FET with 3nm Multi-Nanosheet Structure," The 29th Korean Conference on Semiconductors, Feb. 2022. (Corresponding author)

[43] 김기홍, 김민수, 전현준, 라창호, 전종욱, “강유전체 기반 로직-인-메모리 FeFET 소자의 연산회로 특성 분석,” 대한전자공학회 하계 학술대회, July 2021. (Corresponding author)

[42] 박수길, 김현경, 유창현, 전종욱, “3nm급 Multi-Nanosheet FET 소자의 Bottom Oxide에 따른 SRAM 특성,” 대한전자공학회 하계 학술대회, July 2021. (Corresponding author)

[41] 김민성, 박지훈, 전종욱, “Mono-layer WS2 채널 트랜지스터 회로 특성,” 대한전자공학회 하계 학술대회, July 2021. (Corresponding author)

[40] 오주영, 김다솔, 오종원, 유창현, 전종욱, “저전력 Nanoscale CMOS 기술을 위한 상전이 물질 특성연구,” 대한전자공학회 하계 학술대회, July 2021. (Corresponding author)

[39] 유창현, 전종욱, “3nm급 Multi-Bridge Channel Field Effect Transistor의 Bottom Oxide 및 Package에 따른 Self-Heating 변화,” 대한전자공학회 하계 학술대회, July 2021. (Corresponding author)

[38] 이예지, 장원영, 권경배. 유창현, 전종욱, “3nm급 multi-nanosheet FET의 bottom isolation이 연산회로에 미치는 영향,” 대한전자공학회 하계 학술대회, July 2021. (Corresponding author)

[37] Dasol Kim, JongWon Oh, Yoongeun Seon, and Jongwook Jeon, “Circuit Analysis of Low Power Logic Devices with Phase Change Materials,” The 28th Korean Conference on Semiconductors, Feb. 2021. (Corresponding author)

[36] Changhyun Yoo, Hyunwoo Kim, Yoongeun Seon, and Jongwook Jeon, “Effects of Various Process Options on Self-heating in Multi-Nanosheet FET,” The 28th Korean Conference on Semiconductors, Feb. 2021. (Corresponding author)

[35] Semin Bae, Hyunji Kim, Yoongeun Seon and Jongwook Jeon, “Study on Local Interconnect Resistance at sub-5nm Technology Node,” The 28th Korean Conference on Semiconductors, Feb. 2021. (Corresponding author)

[34] Yeji Kim, Yoongeun Seon, and Jongwook Jeon, “Surface Potential Modeling of Negative Capacitance Gate-All-Around FET with Interface Trap,” The 28th Korean Conference on Semiconductors, Feb. 2021. (Corresponding author)

[33] Jaeyeol Kim, Sanha Lee, Changsun Lim, Kiron Park, Jihun Park and Jongwook Jeon, “Off-State Stress(OSS) Analysis Methodology of MOSFET using TCAD,” The 28th Korean Conference on Semiconductors, Feb. 2021. (Corresponding author)

[32] Dayoung Ahn, Kangryun Kim, Kiron Park, and Jongwook Jeon, “Statistical Time Dependent Dielectric Breakdown Analysis Methodology of 3D Nanoscale Semiconductor Device based on Monte Carlo Simulation,” The 28th Korean Conference on Semiconductors, Feb. 2021. (Corresponding author)

[31] 김재열, 이산하, 임창선, 박지훈, 선윤근, 박기론, 전종욱, “3D TCAD를 활용한 5nm 이하 반도체 소자의 Off-State Stress 분석,” 대한전자공학회 하계 학술대회, Aug. 2020. (Corresponding author)

[30] 김강륜, 안다영, 박기론, 전종욱, “3차원 나노 스케일 반도체 소자의 Time Dependent Dielectric Breakdown 분석 기법,” 대한전자공학회 하계학술대회, Aug. 2020. (Corresponding author)

[29] 김예지, 선윤근, 전종욱, “Negative Capacitance 적용된 Gate-All-Around FET의 Unified I-V 특성 모델 및 소자 특성 분석,” 대한전자공학회 하계학술대회, Aug. 2020. (Corresponding author)

[28] 김다솔, 오종원, 박한솔, 유창현, 김현지, 선윤근, 전종욱, “상전이 물질 기반 저전력 로직 소자의 회로 레벨 분석,” 대한전자공학회 하계 학술대회, Aug. 2020. (Corresponding author)

[27] 손권주, 박기론, 전종욱, “절연막 수명 분석 위한 Monte Carlo기반 Percolation Path 생성 모델,” The 27th Korean Conference on Semiconductors, Feb. 2020. (Corresponding author)

[26] 배다현, 선윤근, 전종욱, “Negative Capacitance 를 적용한 Gate-All-Around 트랜지스터의 동작 영역별 전류 모델,” The 27th Korean Conference on Semiconductors, Feb. 2020. (Corresponding author)

[25] 김수원, 김종민, 선윤근, 전종욱, “3 차원 수직 NAND Cell 의 단일 Grain Boundary 로 인한 산포 특성 연구,” The 27th Korean Conference on Semiconductors, Feb. 2020. (Corresponding author)

[24] Jungmin Hong, Jaewoong Park, Jeawon Lee, Jeonghun Ham, Kiron Park, and Jongwook Jeon, “나노스케일 3 차원 터널링 반도체 소자에서의 Heavy-Ion 효과 분석,” 대한전자공학회 하계 학술대회, p.283, June 2019. (Corresponding author)

[23] Jongmin Kim, Yoongeun Seon, Joohyung Park, Soowon Kim, and Jongwook Jeon, “다결정 실리콘 채널 기반 나노스케일 Gate-All-Around 소자에서의 Grain Boundary 효과,” 대한전자공학회 하계 학술대회, p.120, June 2019. (Corresponding author)

[22] Kiron Park, Sujin Im, and Jongwook Jeon, “온도 의존성을 반영한 개선된 TDDB 수명 예측 모델 개발,” 대한전자공학회 하계 학술대회, p.113, June 2019. (Corresponding author)

[21] Kyul Ko, Yeaji Yoo, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Variability-Aware Simulation of Tapered GAA Vertical FETs,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[20] Yoongeun Seon, Jaehun Kim, Jaehyun Lee, and Jongwook Jeon, “Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Silicon Channel,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Corresponding author)

[19] Jaeyeol Park, Changbeom Woo, Shinkeun Kim, Dongjun Lee, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Optimization of Vertical Nanowire Transistors for 3.5 nm Technology Node,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[18] Yeaji Yoo, Kyul Ko, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Interplay Between Line Edge Roughness and Interface Traps in Nanoplate VFETs,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[17] Heesauk Jhon, Sungho Park, Jaehee Lee, Gwanho Lee, Jongwook Jeon, and Myounggon Kang, “TFET (Tunneling-FET) and CMOS Hybrid Inverter Fabricated in 65nm RF CMOS Technology,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[16] Heesauk Jhon, Taeoh Oh, Sungho Park, Gwanho Lee, Jongwook Jeon, Syed K. Islam, and Myounggon Kang, “900MHz RF to DC Energy Harvesting System Design,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[15] Hyunwoo Kim, Hyunsuk Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Comparison of Self-Heating Effects in 3.5nm Node Nanoplate-FET Using Corner Spacer,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[14] Jongsu Kim, Myounggon Kang, Jongwook Jeon, and Hyungcheol Shin, “Analysis of Hot Carrier Degradation in Short Channel MOSFET according to Temperature,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Co-author)

[13] Kiron Park, Suhyun Kim, Sookyung Park, and Jongwook Jeon, “Development of Time-Dependent-Dielectric Breakdown Analysis Solution,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Corresponding author)

[12] Yoongeun Seon, Jaemin Han, Minsik Choi, Heesauk Jhon, and Jongwook Jeon, “Layout Effect Analysis on Sub-10nm bulk-FinFET’s Thermal Behaviors with Pre-existing EDA Software,” The 26th Korean Conference on Semiconductors, Feb. 2019. (Corresponding author)

[11] Jongwook Jeon, “Physics-based SPICE modeling for phase-change memory cell,” The 25th Korean Conference on Semiconductors, Feb. 2018. (First author)

[10] Jongwook Jeon, Il Han Park, Hyun-Gi Choi, Wookghee Hahn, Kihwan Choi, Sunghee Yun, Gi-Young Yang, Keun-Ho Lee, and  Young-Kwan Park, “Accurate Compact Model of NAND Flash Cell Array,” The 35th Samsung Semiconductor Technology Paper, Oct. 18, 2012. (First author)

[9] Jung Yeol Kim, Changho Han, Sung-Jae Kim, Sunghee Lee, Jongwook Jeon, Sang-Hoon Lee, and Young-Kwan Park, “Model Kit Development for DRAM tRDL Fail-bit Analysis,” The 35th Samsung Semiconductor Technology Paper, Oct. 18, 2012. (Co-author)

[8] Jongwook Jeon, Yunam Yoon, Han-Su Kim, Hansu Oh, and Hyungcheol Shin, “Simple model for the MOSFET channel thermal noise,” The 15th Korean Conference on Semiconductors, pp. 619-620, Feb. 2008. (First author)

[7] MinSuk Koo, Ickhyun Song, Jongwook Jeon, HeeSauk Jhon, and Hyungcheol Shin, “Noise characteristics of mm-wave CMOS low noise amplifier with 65 nm CMOS technology,” The 15th Korean Conference on Semiconductors, pp. 108-109, Feb. 2008. (Co-author)

[6] Bong Chan Kim, Seungwon Yang, Jongwook Jeon, Jinho Kim, and Hyungcheol Shin, “Random noise analysis in CMOS image sensor readout circuit,” The 15th Korean Conference on Semiconductors, pp. 882-883, Feb. 2008. (Co-author)

[5] Yeonam Yun, Jongwook Jeon, Jaehong Lee, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, “RF modeling of ultra-short-channel MOSFETs in subthreshold region,” The 15th Korean Conference on Semiconductors, pp. 399-400, Feb. 2008. (Co-author)

[4] Jongwook Jeon, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin, “A new noise parameter model of RF MOSFETs,” The 14th Korean Conference on Semiconductors, pp. 617-618, Feb. 2007. (First author)

[3] Jongwook Jeon, Hochul Lee, Youngchang Yoon, and Hyungcheol Shin, “Characterization of thermal, 1/f, and RTS noises in 130nm RF CMOS,” 6th Workshop on RF Integrated Circuit Technology, Sept. 2006. (First author)

[2] Jongwook Jeon, Seyoung Kim, In Man Kang, and Hyungcheol Shin, “Analytical modeling of MOSFET's noise parameters for RF circuit design using 0.13um CMOS devices” The 13th Korean Conference on Semiconductors, pp. 823-824, Feb. 2006. (First author)

[1] Jongwook Jeon, Seyoung Kim, In Man Kang, and Hyungcheol Shin, “Thermal noise and noise parameters modeling for RF circuit design using 0.13 um CMOS device,” 5th Workshop on RF Integrated Circuit Technology, Sept. 2005. (First author)