Projects

I worked with Professor Rohit Gurjar during the September 2019 - April 2020 on variations of the secretary problem, and the extension of the secretary problem on Matroids. As a part of this project, I went through literature on a number of variants of this problem through the ages, and identified a number of interesting open problems to work on. I proved an improvement by giving an algorithm for the multiple secretary problem over the state of the art, in a constrained range of values. I also proposed and implemented algorithms to test them practically for other matroids like gammoids, graphic and transversal matroids.

(Image from http://datagenetics.com/blog/december32012/index.html)

As part of our Digital Image Processing course at IIT Bombay, we implemented many image processing algorithms across 5 assignments. The rough distributions are:

Assignment 1 - Transformations, Histogram Matching & Equalization

Assignment 2 - Filtering (Bilateral, Patch-based filter)

Assignment 3 - Segmentation

Assignment 4 - Singular Value Decomposition, PCA, Face Recognition System

Assignment 5 - 2D Fourier Transforms, Image Restoration

All our codes and reports can be found here.

In the course "Microprocessors" at IIT Bombay, we created a 6 staged pipelined processor called IITB-RISC with a given set of 15 instructions. In particular, we optimized for performance by including hazard mitigation techniques and data forwarding mechanisms. We also went on to do the bonus project, which was to implement this in a 2-way fetch manner (full problem statement available here). There were major challenges in this project - the instruction set included instructions such as LM (load multiple), followed by a bitmask such as 00011000, denoting that registers R3-4 were to be loaded. If such an instruction was passed, we were only supposed to use 2 cycles - and thus, our processor had to precompute this and break the instructions into multiple smaller ones. Our entire codes can be found here (extensively tested, single fetch) and here (2 way fetch, LM/SM slightly buggy).

While doing the course "Digital Circuits" at IIT Bombay, we decided to create a small program that can help diagnose stuck-at-0 and stuck-at-1 faults in digital circuits, by providing the appropriate test case which will identify the fault. The input format is the same as taken in by VHDL, thus making it easy to use as an add-on to a program. Porting this to a modern SAT solver will speed up the execution of this code by a lot, and may lead to more practical usability (currently, it helps in debugging small circuits). Code is here.

(Image is taken from https://accendoreliability.com/digital-circuits-stuck-fault-model/)

H.A.N.C.O. is an IoT device developed with a vision to become a dedicated personal AI assistant that we created in our first year. This was a part of the "Institute Technical Summer Project" funding at IIT Bombay. Documentation on HANCO can be found here.