Computer Architecture (CA)
Multi-core Cache Architecture, DRAM Architecture, Hardware Security (Cache Security), Neuromorphic Computing, and Hybrid Memory etc.
Multi-core Cache Architecture, DRAM Architecture, Hardware Security (Cache Security), Neuromorphic Computing, and Hybrid Memory etc.
A significant portion of my research is concentrated on the memory architecture of chip-multiprocessors, also known as CMPs. More than ten years have passed since I began working in this particular field. My primary focus is on enhancing the effectiveness of the Last Level Cache (LLC) for Tiled CMPs (TCMP) and the main memories in terms of both performance and energy usage. During the course of my doctoral studies, I have presented methods that can lower the ratio of missed LLCs in TCMP. Following completion of my doctoral studies, I broadened the scope of my research to include both main memories and non-volatile memories (NVM). My focus has been on the hardware security of CMPs and Main Memories for the past few years. I am actively working on hardware security. An overwhelming majority of the research difficulties that my group is currently working on will be encountered by the processors of the next generation.
===================================
Some common research topics where me and my team is currently working are:
Making the Last Level Cache (LLC) secure from Cache Timing Channel Attacks
How to use Cache Partitioning and Cache Randomization techniques efficiently to prevent timing channel attacks without compromising on performance.
How to detect Covert Channel and Side Channel attack on LLC.
Analyzing the efficiency of the existing attack prevention and detection techniques.
Exploring the possibilities of different types of Hardware Trojans (HT) on the Network-on-Chip (NoC) of modern multicore processors.
Impact on NoC routing in presence of HT in routers and network interfaces.
Incorrect program execution because of the HTs present in NoC.
Possibilities of timing channel attacks through handshaking between HTs and malicious applications.
Making the Non-Volatile Memory Technology efficient and secure for designing the LLC in future multicore processors.
Enhancing the write endurance of STT-RAM based LLCs.
Reducing the overhead of write operations (both latency and energy) in STT-RAM based LLC.
The challenges in making the STT-RAM based LLC secure from timing channel attacks.
Proposing efficient hybrid LLC structure.
Designing LLC with Multi-retention based STT-RAM.
Enhancing the performance and energy consumption of cache and main memories
Replacement policies, Efficient cache utilization, Coherence protocol, NUCA: Static NUCA and Dynamic NUCA, Cache partitioning, Main memory, Refresh overhead of DRAM based memories.
Efficient cache resizing to optimize the energy consumption of LLC.
[Approved] Do not Forget Cache Content Management Policies while Designing Secure Last-level Cache- under Core Research Grant of SERB (CRG), Govt. of India. ==> Budget 25L.
[Ongoing] Efficient Use of STTRAM for Designing Secure Last Level Cache of Modern Chipmultiprocessors- under Seed Grant, IIT Hyderabad ==> Budget 30L.
[Completed] Efficient Utilization and Refresh Overhead Minimization of eDRAM based Last Level Cache - SERB, Govt. of India (EMEQ) ==> Budget 35 L .
[Completed] Secured Shared Cache Memory Architecture for Modern Multicore Processors, ISIRD (IIT Ropar Seed Grant), ==> Budget 10 L
[Completed] Reducing Energy Consumption and Operating Temperature of Last Level DRAM Cache in Multicore Systems - under Early Career Research Grant (ECR) of SERB, Govt. of India. ==> Budget 15L.
I have opportunities for PhD, JRF, and intern positions. If you're interested, you can reach out to me via email for more information. Please only email me if your interests align with mine, as I may not respond otherwise. Internship applicants are encouraged to read about my research interests before applying.
Entry level skills required to work with me: Good knowledge in C/C++, Basics of Computer Architecture, Basics of Data Structures.
Additional skills required (not essentials): Advanced Computer Architecture, Basic concept of Digital Logic Design.
I give everyone joining me at least three weeks to understand the basics. I offer online resources to help with quickly grasping the necessary fundamentals. It's okay if you don't have advanced knowledge in my research area when you start. What's important is that you are dedicated and motivated to work in this field.