My List of Publications

Journals:

1. Prabuddha Sinha, Krishna Pratik Bv, Shirshendu Das and Venkata Kalyan Tavva, "SmartDeCoup: Decoupling the STT-RAM LLC for even Write Distribution and Lifetime Improvement " Elsevier Journal of System Architecture, Accepted (JSA), February 2025.

2. Prabuddha Sinha, Mangena Likhit Sai, Shirshendu Das, and TV Kalyan, "TENDRA: Targeted Endurance Attack on STT-RAM LLC", IEEE Embedded Systems Letters (ESL), Accepted, Nov 2024

3. Atul Kumar, Shirshendu Das and Basant Subba, "HTree: Hardware Trojan Attack on Cache Resizing Policies", IEEE Embedded Systems Letters (ESL), Accepted, Dec 2023

4. Jaspinder Kaur and Shirshendu Das, “RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Accepted, Nov 2023. 

5. Atul Kumar, Dipika Deb, Shirshendu Das, and Palash Das, "edAttack: Hardware Trojan Attack on On-Chip Packet Compression", IEEE Design and Test journal, accepted through NOCS 2023.

6. Jaspinder Kaur and Shirshendu Das, "TPPD: Targeted Pseudo Partitioning based Defence for Cross-Core Covert Channel Attacks", Elsevier Journal of System Architecture, Accepted (JSA), December 2022.

7. Divyansh S. Maura, Tanmay Goel, Kaustav Goswami, Dip Sankar Banerjee, and Shirshendu Das, "Variation Aware Power Management for GPU Memories",  Elsevier Journal of Microprocessors and Microsystems (MICPRO), Accepted, Oct 2022.

8. Bharat Bisht, and Shirshendu Das, "BHT-NoC: Blaming Hardware Trojans in NoC Routers", IEEE Design and Test journal, Accepted through NOCS 2022.

9. Sudershan Kumar, Prabuddha Sinha, and Shirshendu Das, ''WinDRAM: Weak Rows as in-DRAM Cache", Journal of Concurrency and Computation: Practice and Experience, Accepted on July 2022.

10. Bindu Agarwalla, Shirshendu Das and Nilkanta Sahu, "Process Variation Aware DRAM-Cache Resizing", Elsevier Journal of System Architecture, Accepted (JSA), November 2021.

11. Jaspinder Kaur and Shirshendu Das, "A Survey on Cache Timing Channel Attacks for Multicore Processors ", Journal of Hardware and Systems Security, Accepted, April 2021. A read-only version is available here: https://rdcu.be/ckXf2

12. Kaustav Goswami,  Dip Sankar Banerjee and Shirshendu Das, "Towards Enhanced System Efficiency While Mitigating Row Hammer", ACM Transactions on Architecture and Code Optimization (TACO), Accepted, March 2021.

13. Bindu Agarwalla, Shirshendu Das and Nilkanta Sahu, "Efficient Cache Resizing Policy for DRAM-based LLCs in ChipMultiprocessors", Elsevier Journal of System Architecture (JSA), Accepted, September 2020.

14. Dipika Deb, John Jose , Shirshendu Das and H. K. Kapoor, “Cost Effective Routing Techniques in 2D Mesh NoC using On-Chip Transmission Lines,” Elsevier Journal of Parallel and Distributed Computing (JPDC), Vol. 123, 118-129, 2019.

15. Shirshendu Das and H. K. Kapoor, “Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets,” IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(8), 2017, 2229-2243. 

16. Shirshendu Das and H. K. Kapoor, “A Framework for Block Placement, Migration and Fast Searching in Tiled-DNUCA Architecture,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 2016. 

17. Shirshendu Das and H. K. Kapoor, “Victim Retention for Reducing Cache Misses in Tiled Chip Multiprocessors,” Journal of Microprocessors and Microsystems (Elsevier), 38 (4), (2014), 263–275. 

18. Shirshendu Das, P. S. Duggirala, and H. K. Kapoor, “A formal framework for interfacing mixed-timing systems,” Integration, the VLSI Journal (Elsevier), 46 (3), (2013). 255-264. 

19. H. K. Kapoor, P. Kanakala, M. Verma, and S. Das, “Design and formal verification of a hierarchical cache coherence protocol for noc based multiprocessors,” The Journal of Supercomputing (Springer), 65 (2), 2013, 771-796. 

Conferences:

1. Prathamesh Nitin Tanksale, Guru Raghav S. Seethiraju, Shirshendu Das and Venkata Kalyan Tavva, "RRR : Rethinking Randomized Remapping for High Performance Secured NVM LLC", IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2025.

2. Prabuddha Sinha, Krishna Pratik Bv, Shirshendu Das and Venkata Kalyan Tavva, "LiveWay: Dynamic Write Bypassing for Lifetime Enhancement in STT-RAM LLC" Student Research Symposium of HiPC, 2024.

3. Prabuddha Sinha, Krishna Pratik Bv, Shirshendu Das and Venkata Kalyan Tavva, "PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC", The International Symposium on Memory Systems (MEMSYS), 2024.

4. Aditya S Gangwar, Prathamesh N Thanksale, Shirshendu Das, and Sudeepta Mishra, "Flush+earlyReload: Covert Channels Attack on Shared LLC Using MSHR Merging",  Design, Automation and Test in Europe Conference (DATE) 2024.

5. Prathamesh N Thanksale, Kousik Kumar Dutta, Shirshendu Das, and T. V. Kalyan, "CAMOUFLAGE: An Efficient Mechanism to Hide Congestion in NVM LLC", Extended Abstract in HiPC 2023.

6. Prabuddha Sinha, Krishna Prathik, Shirshendu Das, and T. V. Kalyan, "Hide-n-Seek: Hiding Writes in Buffer for Lifetime Improvement in STT-RAM based LLC", Extended Abstract in HiPC 2023.

7. Atul Kumar, Dipika Deb, Shirshendu Das, and Palash Das "edAttack: Hardware Trojan Attack on On-Chip Packet Compression ", International Symposium on Networks-on-Chip (NOCS) 2023, in association with IEEE Design and Test journal.

8. Jaspinder Kaur, and Shirshendu Das, "ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning," 24th International Symposium on Quality Electronic Design (ISQED), San Francisco, California, USA, 2023.

9. Kaustav Goswami, Shirshendu Das, Sagar Satapathy and Dip Sankar Banerjee, "A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices", The International Symposium on Memory Systems (MEMSYS), 2022.

10. Samiksha Verma and Shirshendu Das, "Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly", The International Symposium on Memory Systems (MEMSYS), 2022.

11. Bharat Bisht, and Shirshendu Das, "BHT-NoC: Blaming Hardware Trojans in NoC Routers", International Symposium on Networks-on-Chip (NOCS) 2022, in association with IEEE Design and Test journal.

12. Manaal M. Jamadar, Jaspinder Kaur and Shirshendu Das, "MAPCP: Memory Access Pattern Classifying Prefetcher", The International Symposium on Memory Systems (MEMSYS), 2021.

13. Shobhit Kumar, Manaal M. Jamadar, Jaspinder Kaur and Shirshendu Das, "Efficient On-Chip Communication for Neuromorphic Systems", The 21th IEEE International Conference on Scalable Computing and Communications (ScalCom 2021), 2021, Atlanta, USA.

14. Tanmay Goel, Divyansh Maura, Kaustav Goswami, Shirshendu Das and Dip Sankar Banerjee, "Towards Row Sensitive DRAM Refresh through Retention Awareness", ISQED 2021.

15. Kousik Kumar Dutta, Prathamesh Nitin Tanksale and Shirshendu Das, "A Fairness Conscious Cache Replacement Policy for Last Level Cache", Design, Automation and Test in Europe Conference (DATE) 2021.

16. Anurag Agarwal, Jaspinder Kaur and Shirshendu Das, "Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache", Design, Automation and Test in Europe Conference (DATE) 2021. - Nominated for best paper award.

17. Angelic, Megha Mahobe, Jaspinder Kaur, Shirshendu Das, "Near Data Processing and its Applications", 6th international conference on Soft Computing Theories and Applications (SoCTA-21), 2021.

18. Shobhit Kumar, Shirshendu Das, Gourav Badone, Amit Kumar, "A Survey on Efficient Interconnects for Neuromorphic Systems", 6th international conference on Soft Computing Theories and Applications (SoCTA-21), 2021.

19. Kaustav Goswami, Hemanta Kumar Mondal,Shirshendu Das and Dip Sankar Banerjee, "State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency," International Symposium on Quality Electronic Design (ISQED), Santa Clara California, USA, 2019.

20. Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor, "Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors," VLSI Design 2018, 31-36.

21. Shirshendu Das and Hemangee K. Kapoor, "Latency Aware Block Replacement for L1 Caches in Chip MultiProcessors," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Bochum, Germany.

22. Shirshendu Das and Hemangee K. Kapoor, "Dynamic Associativity Enabled DNUCA to Improve Block Localisation in Tiled CMPs," 31st ACM/SIGAPP Symposium On Applied Computing (ACM-SAC), 2016, Pisa, Italy.  

23. Shounak Chakraborty, Shirshendu Das and Hemangee Kapoor, "Static Energy Efficient Cache Reconfiguration for Dynamic NUCA in Tiled CMPs," 31st ACM/SIGAPP Symposium on Applied Computing (ACM-SAC), 2016, Pisa, Italy.

24. Shirshendu Das and Hemangee K. Kapoor, "Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches," 29th International Conference on VLSI Design-2016 (VLSID), 2016, Kolkata, India.

25. Shounak Chakraborty, Shirshendu Das and Hemangee K. Kapoor, "Performance constrained static energy reduction using way-sharing target-banks," 17th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM), in conjunction with IPDPS, 2015, Hydrabad, India.

26. Shirshendu Das and Hemangee K. Kapoor, "Dynamic Associativity Management Using Utility Based Way-Sharing," 30th ACM/SIGAPP Symposium On Applied Computing (ACM-SAC),2015, Salamanca, Spain.

27. Hemangee Kapoor, Shirshendu Das and Shounak Chakraborty, "Static energy reduction by performance linked cache capacity management in Tiled CMPs," 30th ACM/SIGAPP Symposium on Applied Computing (ACM-SAC), 2015, Salamanca, Spain.

28. Shirshendu Das and Hemangee K. Kapoor, "Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs," 28th International Conference on VLSI Design (VLSID), 2015, Bangalore, India.

29. Mojjada Lakshmi Prasad, Shirshendu Das and Hemangee K. Kapoor, "An Approach for Multicast Routing in Networks-on-Chip," 13th International Conference on Information Technology (ICIT), 2014, Bhubaneswar, India.

30. Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor, "Towards a Better Cache Utilization Using Controlled Cache Partitioning," 11th IEEE International Conference on Embedded Computing (EmbeddedCom), 2013, Chengdu, China. 

31. S. Das and H. K. Kapoor, "Dynamic associativity management using fellow sets," 4th International Symposium on Electronic System Design (ISED), 2013, NTU Singapore.