VLSI Physical Design

PDN design for mixed macro blocks and standard cells

Macro blocks already have partial PDN, while standard cells do not. So the design, which has been placed, is divided into a number of partitions: each macro block in its own partition, and standard cell area into a number of partitions. Multi-layer PDN synthesis is performed in each partition one by one; the goal of this problem is to insert minimum number of metal straps (in irregular pitches) while IR drop and electromigration (EM) constraints are respected. In a heuristic method, PDN straps are inserted in each metal layer (from lowest toward highest) assuming that IR drop is constrained by some amount in each layer;

Decap Insertion with Local Cell Relocation

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Decaps become more complex these days while a number of metal layers are used for internal connection, thereby starting to manifest themselves as routing blockage. Post-placement decap insertion with both IR-drop violations and routing design rule violations (DRVs) being taken into account is addressed for the first time. Local cell relocation is performed in an effort to reduce the number of decaps in actual decap insertion step. U-Net integrated with graph convolutional network is introduced to predict the DRV probability, which drives decap insertion. The problem of decap insertion is then formulated as mixed integer quadratically constrained programming and a heuristic algorithm is presented for practical application. Experiments with a few test circuits demonstrate that the increase in routing DRV is reduced by 26% on average with no IR-drop violations, compared to conventional methods that do not explicitly consider DRVs. This brings 60% reduction in routing runtime and 33% improvement in total negative slack.