Machine Learning for CAD

Timing parameter interpolation using R-CNN

Interpolation is used to approximate the timing parameters of logic cells not specified in timing tables. Bilinear interpolation has been taken for granted in the industry, but the error increases as the non-linearity of the timing parameters increases. In this paper, we propose machine learning (ML) based interpolation to obtain more accurate timing parameters. Recurrent convolutional neural network (R-CNN) is employed and various ranges of table entries form a sequence of input data, in which the recurrent network allows them to influence the interpolation. In addition, variational auto-encoder (VAE) is used to capture the distribution feature of the table. ML interpolation is parallelized in GPU to minimize the runtime overhead from numerous arithmetic operations. Experimental results demonstrate that ML interpolation reduces timing parameter error by 19.7% and path delay error by 3.4% compared to bilinear interpolation at the cost of 13% runtime overhead.

Post-placement PDN optimization using HLA-GCN

Power distribution network (PDN) is typically constructed with regular straps in the industry. After cell placement, PDN optimization removes a partial strap repeatedly from the regular PDN to minimize routing congestion overflows while honoring IR-drop constraint. The layout is first divided into several partitions, and each partition is subdivided again into sub-partitions. We sequentially select a partition and a sub-partition within it, in which some candidates are classified using hierarchical layout-aware graph convolutional network (HLA-GCN) and one candidate is chosen among them by a score of the number of overflows and maximum IR-drop. In the selected sub-partition, we try to remove each partial strap one by one and select the best one considering actual impact on IR-drop and routing congestion.

Routability optimization of extreme aspect ratio design using CNN and U-Net+GAT 

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. Two routability optimization methods are used to implement designs even with very low (or high) aspect ratio and high area utilization. First, we find the best assignment of non-uniform placement utilization through convolutional neural network model, and cell placement is performed while respecting the placement utilization. This allows many cells to be spread out over the entire design rather than being centered. In the second, some flip-flops are selectively stacked to reduce the routing resources used for clock routing. U-Net model is built with graph attention network (GAT) to predict the congestion after clock tree synthesis, and the flip-flops in highly congested areas are selected for stacking.