Design Methodology for Advanced Technology

Airgap insertion and layer reassignment

Airgap formed in inter-metal dielectric (IMD) reduces coupling capacitance, and thus can be utilized for timing optimization. Metal layers with airgap are limited due to high cost of airgap formation. Layer reassignment is to relocate some timing critical wires in non-airgap layers to airgap layers while non-critical wires in airgap layers are reassigned to non-airgap layers. Airgap insertion is to determine the amount of airgaps that are inserted for each critical wires in airgap layers. The two problems are solved in unified fashion with a goal of maximizing setup total negative slack (TNS) while satisfying hold constraints and design rules. For practical application, a heuristic algorithm is presented and the algorithm is parallelized for application to larger circuits.

Automatic insertion of airgap with design rule constraints

Airgap is constrained by a number of design rules. Manual insertion of airgap while design rules are all respected is inconvenient and time-consuming. We address automatic airgap insertion in this paper, in which the goal is to insert maximum amount of airgap in selected paths (e.g. timing critical paths) while related design rules are all honored. Our approach consists of three steps: (1) layout is decomposed into a set of sublayouts, such that airgap can be inserted in each sublayout independently, (2) each of large sublayouts is further partitioned in heuristic fashion, and (3) airgap insertion in each sublayout (or each partition of sublayout) is performed through ILP (integer linear programming). 

Selective use of stitch-induced via (SIV)

Stitch-induced via (SIV) is introduced to reduce the number of V0 masks. It involves the redesign of standard cells to replace some vias in V0 layer with SIVs, such that the remaining vias can be assigned to the reduced masks. Since SIV formation requires metal stitches in different masks, SIV replacement and metal mask assignment should be solved simultaneously. In the second sub-problem, inter-row via conflict aware detailed placement is addressed. Single row placement optimization is performed for each row to remove metal and inter-row via conflicts, while minimizing cell displacements. Since it is time consuming to consider many cell operations at once, we apply a few operations iteratively, where different operations are applied to each iteration and to each cell depending on whether the cell has a conflict in the previous iteration. Remaining conflicts are then removed by mapping conflict cells to white spaces. To this end, we minimize the number of cells to move and maximize the number of large white spaces before mapping.