Researches

VLSI Physical Design

• PDN design for mixed macro blocks and standard cells

• Decap insertion with local cell relocation

• Initial parameter sampling for timing parameter exploration

• Post-route timing-aware PDN optimization

• Pin optimization for 3D-IC packaging

• Fast thermal analysis and IR-drop analysis models for 3D-IC design (in progress)

• PIM tile place & route algorithms (in progress)

Machine Learning for CAD

• ML-based gate delay calculation

• Library index optimization for accurate interpolation of timing parameters (diffusion model)

• Accurate library parameter interpolation (R-CNN) 

• Post-placement PDN optimization (HLA-GCN)

• Routability optimization of extreme aspect ratio design (CNN and U-Net+GAT)

• Fast analog IR-drop prediction (RS-GCN & Y-Net)

• RL-based temperature-aware floorplanning for 3D-IC (in progress)

Standard Cell Design, Optimization, and Characterization

• Library characterization for custom cells with strong non-monotonic timing characteristics

• Fast timing library characterization through selective use of regression models

• Library tool parameter exploration

• Automatic library error correction

• Leakage optimization using mixed-Vth cells

• Efficient timing library characterization of standard cells using index removal algorithm

• Corner library prediction using ML models (in progress)

Design Methodology for Advanced Technology

• Airgap insertion and layer reassignment

• Automatic insertion of airgap with design rule constraints

• Redundant via insertion for self-aligned double patterning (SADP)

• Selective use of stitch-induced via (SIV)