PDN design for mixed macro blocks and standard cells
Decap insertion with local cell relocation
Post-route timing-aware PDN optimization (in progress)
Fast thermal analysis and IR-drop analysis models for 3D-IC design (in progress)
Pin optimization for 3D-IC packaging (in progress)
PIM tile place & route algorithms (in progress)
Initial parameter sampling for design space exploration (in progress)
Accurate library parameter interpolation (R-CNN)Â
Post-placement PDN optimization (HLA-GCN)
Routability optimization of extreme aspect ratio design (CNN and U-Net+GAT)
Fast analog IR-drop prediction (RS-GCN & Y-Net)
RL-based temperature-aware floorplanning for 3D-IC (in progress)
Standard Cell Design, Optimization, and Characterization
Fast timing library characterization through selective use of regression models
Library characterization for custom cells with strong non-monotonic timing characteristics
Leakage optimization using mixed-Vth cells
Library index optimization for accurate interpolation of timing parameters
Efficient timing library characterization of standard cells using index removal algorithm
Corner library prediction using ML models (in progress)
Library tool parameter exploration (in progress)
Automatic library error correction (in progress)
Design Methodology for Advanced Technology
Airgap insertion and layer reassignment
Automatic insertion of airgap with design rule constraints
Selective use of stitch-induced via (SIV)