Standard Cell Design, Optimization, and Characterization

Fast timing library characterization through selective use of regression models

Timing behavior of standard cells is represented as two-dimensional tables in a timing library, where each table entry is obtained through transistor-level simulation. As technology scales, the number of design corners and standard cells has increased dramatically, leading to a substantial increase in simulation time for timing characterization. This may delay the design schedule or impose additional demands on tool licenses. To address this challenge, we propose a fast timing characterization method that selectively uses transistor-level simulation and model-based prediction. In this method, a subset of table entries is obtained through simulation, while the remaining entries are predicted by regression models trained on the simulated data. Multiple regression models are employed to capture the diverse characteristics of each entry location, and the most accurate model for each entry is identified at one corner, called an anchor corner. The selected models are then used to predict the corresponding entry at target corners. Experimental results show that the proposed method achieves high accuracy with a 40% reduction in runtime; the mean and 3-sigma absolute errors are 0.4% and 2.3%, respectively, representing a significant improvement over conventional methods. The accuracy of the proposed method is further validated on 7-nm technology libraries.

Leakage optimization using mixed-Vth cells

Multiple threshold voltage (multi-Vth) optimization reduces leakage by replacing low-Vth cells with high-Vth cells but is limited by tight design constraints and timing violations on critical paths. This paper proposes a novel approach using mixed-Vth cells, where pull-up and pull-down networks are independently optimized for different Vth types. By selectively assigning higher Vth to only one of the networks, the proposed method achieves significant leakage reduction without violating timing constraints. The methodology ensures to satisfy the constraint of minimum implant width through localized cell relocation. Experimental results show a reduction in leakage power by 22% on average without timing violation in practical runtime, while the conventional cell-based method reduces 10% of leakage.