Members

Jinil An (안진일)

M.S. Candidates, VLSi CAD Lab., Sejong UNIV.

Office: Chungmugwan 501B, Department of Semiconductor Systems Engineering, Science and Technology, 209, Neungdong-ro, Gwangjin-gu, Seoul, Republic of Korea

Personal Information

• Date of Birth : April, 3rd, 1998

• Place of Birth : Seoul, Korea

• Hobby : Visiting good restaurants

• E-mail : blake980403@gmail.com

Awards and Honors

• 제 24회 반도체 설계 대전, 한국반도체산업협회장상, Aug. 2023.

• 제 10회 대한민국 SW융합 해커톤 대회, 정보통신진흥원상, Aug. 2023.

Education

• Sorabol High Sch (Mar. 2014 - Feb. 2017)

• B.S. Cheong-Ju University, Dept of Electronic Engineering (Mar. 2018 - Jul. 2023)

• M.S. Sejong University, Dept of Semiconductor Systems Engineering (Sep. 2023 -)

Conference

• "Mixed-Vth 셀을 활용한 누설전력 최적화 알고리즘",  Korean Conference of Semiconductors (KCS), Jan. 2024