Members

Chanjin Kim (김찬진)

M.S. Candidates, VLSi CAD Lab., Sejong UNIV.

Office: Chungmugwan 501B, Department of Semiconductor Systems Engineering, Science and Technology, 209, Neungdong-ro, Gwangjin-gu, Seoul, Republic of Korea

Personal Information

• Date of Birth : April, 27th, 1997

• Place of Birth : Seoul, Korea

• Hobby : Swimming, Skiing

• E-mail : ckswls97@naver.com

Education

• Sorabol High School (Mar. 2013 - Feb. 2016)

• B.S. Sejong University, Dept of Artificial Intelligence (Mar. 2021 - Feb. 2025)

• M.S. Sejong University, Dept of Semiconductor Systems Engineering (Mar. 2025 -)

Publications

• 김찬진, 정영광, 현대준, "Bayesian optimization 기반 timing table index 최적화," Korean Conference of Semiconductors (KCS), Feb. 2025.

• Younggwang Jung, Chanjin Kim, and Daijoon Hyun, "Library index optimization through diffusion model for accurate timing interpolation," Proc. Int'l Symp. on Circuits and Systems (ISCAS), accepted.