Members

Yujin Lee (이유진)

M.S., VLSi CAD Lab., Sejong UNIV.

Office: Woojungdang 104, Department of Semiconductor Systems Engineering, Science and Technology, 209, Neungdong-ro, Gwangjin-gu, Seoul, Republic of Korea

Personal Information

• Date of Birth : August, 2nd, 2000

• Place of Birth : Cheongju, Korea

• Hobby : Reading book

• E-mail : uzin0802@gmail.com

Education

• Cheong-Ju Osong High School (Mar. 2016 - Feb. 2019)

• B.S. Cheong-Ju University, Dept of Electronic Engineering (Mar. 2019 - Feb. 2023)

• M.S. Cheong-Ju University, Dept of Electronic Engineering (Mar. 2023 - Sep. 2023)

• M.S. Sejong University, Dept of Semiconductor Systems Engineering (Sep. 2023 - Feb. 2025)

Conference

• "비아 필라를 사용한 전력 분배망 최적화," 한국정보기술학회, Jun. 2023.

• "회로 면적 감소를 위한 스탠다드 셀의 렉틸리니어 형태 재설계," Korean Conference of Semiconductors (KCS), Feb. 2023.