Members

Jungsik Song (송정식)

M.S., VLSi CAD Lab., Sejong UNIV.

Office: Woojungdang 104, Department of Semiconductor Systems Engineering, Science and Technology, 209, Neungdong-ro, Gwangjin-gu, Seoul, Republic of Korea

Personal Information

• Date of Birth : February, 2nd, 1999

• Place of Birth : Jeju, Korea

• Hobby : Watching movie

• E-mail : thdwjdtlr123@naver.com

Education

• Cheong-Ju Jusung High School (Mar. 2014 - Feb. 2017)

• B.S. Cheong-Ju University, Dept of Electronic Engineering (Mar. 2017 - Feb. 2023)

• M.S. Cheong-Ju University, Dept of Electronic Engineering (Mar. 2023 - Sep. 2023)

• M.S. Sejong University, Dept of Semiconductor Systems Engineering (Sep. 2023 - Feb. 2025)

Awards and Honors

• 제 24회 반도체 설계 대전, 한국반도체산업협회장상, Aug. 2023.

• 제 10회 대한민국 SW융합 해커톤 대회, 정보통신산업진흥원상, Aug. 2023.

• An oral presentation at KCS, titled "전력분배망 최적화를 위한 고속 전압 강하 분석," is selected to receive Corporate Award (Samsung Award) (2023.05.30)

Conference

• "전력분배망 최적화를 위한 고속 전압 강하 분석," Korean Conference of Semiconductors (KCS), Feb. 2023

• "타이밍 제약조건을 고려한 전력분배망 최적화",  Korean Conference of Semiconductors (KCS), Jan. 2024