Good vs Bad Design Practices Board
Overview
In this board that I designed, there is a 5 V input that is converted to 3.3 V, which is then used to power a 555 timer. The 555 timer generates a 60% duty cycle signal, which is then fed to a hex inverter. In the initial design, I made some mistakes on purpose by implementing bad design practices. For instance, I connected all the grounds into one point, removed the common return plane, and placed the decoupling capacitor far away from the IC, which resulted in a high loop inductance. To demonstrate the effects of bad design practices and measurements, I compared it to a good design that features a small loop inductance as close to the IC as possible and a common return plane. This greatly reduces noise in the power rail and ground bounce, which can be measured in the quiet high and quiet low of the hex inverters.
Schematic layout
PCB Layout
assembled PCB
Bare PCB
ground bounce in the rising edge good vs bad
power rail noise good vs bad
rise vs fall 555, hex 555 inverted output good vs bad
555 timer rising edge good vs bad layout
Detailed report included below
