Faculty
Prof. Pradeep Dixit
Dr. Pradeep Dixit is an Associate Professor in the Department of Mechanical Engineering, IIT Bombay. Prior to joining IIT Bombay in March 2015, Pradeep was working as a senior researcher in the Technical Research Center of Finland (VTT), where he was responsible for the development of 3D packaging technology for MEMS packaging applications. Pradeep has earned his masters and PhD degree from IIT Bombay and Nanyang Technological University (NTU) Singapore in year 2003 and 2008, respectively. At NTU, he developed a high aspect ratio DRIE etched copper filled through-Silicon Vias. He received Norman Hackermann Young Author Award in 2006 for his work on aspect ratio dependent copper filling process. In his postdoctoral fellowship, He worked with Prof. Rao Tummala in Packaging Research Center at Georgia Tech.
He has published more than 65 articles in peer-reviewed journals. His research interests are in the MEMS fabrication, 3D Packaging, Through-substrate vias (TSV) and Micromachining for difficult-to-machine materials.
Prof. Pradeep Dixit has recently joined the editorial board of Microsystem Technologies, where he is one of the Associate Editors.
Research Interests:
Micro-Electro-Mechanical-Systems (MEMS) fabrication, Sensors & Actuators,
Microsystems Packaging, Through-Silicon Vias based 3D Interconnects
Non-Conventional Machining for difficult-to-machine materials
Electrochemical discharge machining, Electrochemical/Electrodischarge machining
Google Scholar profile:
Education
Ph.D
Nanyang Technological University, Singapore, 2008
M.Tech
Indian Institute of Technology Bombay, 2003
B.Tech
Madan Mohan Malviya University of Technology, 2001
Professional Experience
1. Associate Professor, Department of Mechanical Engineering, IIT Bombay, March 2015 - till now
2. Senior researcher, VTT Technical Research Center of Finland January 2009-January 2015
Responsibilities:
Task leader of developing Through-Silicon Vias (TSV) technology for MEMS Integration and Packaging for various EU-Projects
Knowledge in Silicon/Silicon oxide Plasma etching, copper electrodeposition technology, Embeded Integrated passive devices (IPD).
Development of Copper electroplated tapered Through-Silicon Vias (TSV) for wafer-level packaging of MEMS resonator (Project: Go4Time, WiserBAN, EU-ESiP)
Fabrication and characterization of Via-first poly Silicon filled TSVs (Project: EU-E3CAR)
Thermo-mechanical characterization of copper filled TSVs (Project: EU-ESiP)
Planarization and chemical-mechanical polishing for Silicon, SiO2 and Germanium materials
Postdoctoral fellow, Packaging Research Center, Georgia Tech USA, January 2008 - January 2009
Responsibilities:
Through-Silicon Vias (TSV) technology development for 3D Interconnection
TSV based Wafer-level Packaging applications
Graduate research student, Nanyang Technological University Singapore, July 2004 - December 2007
Through-Silicon Vias (TSV) technology for MEMS Integration and Electronic Packaging
Development of high aspect ratio via formation by plasma etching
Software engineer, Syntel India Limited, March 2003 - June 2004
Courses Taught at IIT Bombay
UG Core courses:
ME 338 : Manufacturing Processes II (Spring semester 2016, '17, '18, '19, '20, '21, '22)
ME 221 : Structural Materials (Autumn 2023)
ME206 : Manufacturing Processes I (Spring semester 2020, '21, '22)
ME119 : Engineering Drawing (Spring semester 2016, '17, '18, Autumn 2016, Autumn '20)
PG Elective Courses:
ME 768 : Introduction to Microsystems Packaging (Autumn semester 2017, '18, '19)
ME 645 : MEMS - Design, Fabrication, and Characterization (Autum semester 2016, Spring semester 2016, '17, '18, '19, '22)
Labs Courses:
ME 374: Manufacturing Processes Lab ( Spring Semester 2019, 22, 23)
Courses Taught at IIT Goa and IIT Dharwad (Visiting Professor)
ME 115 : Engineering Drawing (Autumn Semester Jan - Apr 2018, IIT Goa)
ME 338 : Manufacturing Process II (Spring Semester July - Sep 2018, IIT Dharwad)