Artificial intelligence is transforming every aspect of modern life—from autonomous vehicles and robotics to healthcare, communications, and scientific discovery. Yet the next generation of intelligent systems will not be limited by algorithms alone. Their future depends on breakthroughs in the materials and devices that power them.
At the Nanoelectronics Device Research Laboratory (NDRL), we develop we develop next-generation semiconductor materials, nanoscale devices, and AI-enabled design methodologies that redefine how future electronic systems store, process, and communicate information. Our research spans the full innovation pipeline—from material discovery and device physics to circuit technologies and AI-driven semiconductor design.
Our vision is to enable a new generation of energy-efficient computing and communication platforms through four closely connected research directions: Emerging Memory & Logic, RF and Wireless Electronics, Novel Computing and AI for Semiconductor Research (Digital Twins). By combining fundamental science with practical engineering, we aim to accelerate the technologies that will power the intelligent systems of tomorrow.
I’m honored and grateful to receive the NSF CAREER Award titled “CAREER: Monolithic 3D Oxide Semiconductor Nanoelectronics for Energy-Efficient Computing”. The recognition is deeply meaningful, not as an individual achievement, but as a reflection of the many mentors, collaborators, students, and colleagues who have shaped this journey. I’ve been fortunate to learn from and work alongside people who constantly push the boundaries of science and engineering. I’m especially thankful to my wonderful students and collaborators, this work is truly a team effort.
Read the full story to learn more about the research, impact and vision behind this: https://lnkd.in/gFPvvKxU
What if reliability design margins weren’t dictated by over-conservative statistics? Conventional stress-testing requires extensive data across large device populations, often resulting in large guard bands and suboptimal system-level performance. Our paper "Accelerated Reliability Characterization of Ferroelectric Capacitors using Physics-Informed Bayesian Active Learning" combines reliability physics with Bayesian active learning in a closed-loop characterization framework that adaptively selects stress conditions to maximize information gain while minimizing experimental cost—enabling accurate 3σ tail estimation with far less experiments and orders-of-magnitude improvements in bit error rate prediction for emerging memories.
Congrats to Tanvir on his first conference paper titled "Design Space Exploration of Oxide Semiconductor-Based Monolithic 3D Gain Cell Memory" at the 50th European Solid-State Electronics Research Conference (ESSERC) in Bruges, Belgium. Catch us presenting our work!