We are living in an era where edge applications, from self-driving cars to drones and wearable devices, are generating and processing staggering amounts of data in real time. To put it in perspective, a single autonomous vehicle can create nearly 40 terabytes of data every hour, the equivalent of streaming about 6,000 Netflix movies. Making sense of this flood of information with large AI models requires chips that can store, compute, and communicate data quickly and efficiently. Unfortunately, today’s hardware is hitting serious roadblocks. With on-chip memory (SRAM) scaling slowing down, frequent trips need to be made to larger off-chip memory (DRAM2). However, each trip causes serious energy and latency penalty. Meanwhile, as chips for logic, memory, analog, and power delivery are placed side-by-side on a 2D substrate, signals must travel long distances through increasingly resistive interconnects, wasting energy, adding delay, and even causing voltage drops. These inefficiencies limit the ability of current systems to keep up with the demands of AI-driven applications. 

Our research group aims to break past these limitations by exploring new materials and building novel nanoscale devices that can boost on-chip memory density, enhance communication and allow designing 3D integrated circuits with vertically stacked logic, memory, analog and power circuits. I believe this vision represents the ultimate form of scalable, energy-efficient edge computing. It has the potential to transform technologies ranging from autonomous navigation and defense robotics to healthcare diagnostics and disaster response, enabling systems that are faster, smarter, and more reliable right at the edge where data is created.

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