Keynote Talks

Abstract

Functional verification is one of the dominant costs in modern chip development, yet most LLM-for-EDA work stops at artifact generation — Verilog or assertions evaluated on small, open-source designs — rather than closing the loop of executing, triaging, and iterating on real industrial IP. This talk presents a case study of a fully autonomous agentic verification workflow built with NVIDIA around Cadence ChipStack AI SuperAgent, orchestrated by Codex (GPT-5.5) inside a sandboxed NVIDIA OpenShell runtime that drives Cadence Xcelium simulation and Cadence Jasper formal verification. From only high-level natural-language objectives, the system builds design mental models, plans and generates SystemVerilog testbenches and formal properties, runs them against designs, triages failures, and persists auditable artifacts at every stage. We evaluate it on two industrially relevant proof points — a protocol-rich CPIPE block and a smaller APB-to-control bridge — across seven metric axes that mirror DV sign-off. We share central findings, directional productivity evidence, the failure modes that matter most, and what it takes to actually trust an autonomous verification agent.