Keynote Talks

Beyond Code Generation: A Case Study of Long-Running Agentic AI for Industrial Chip Verification

Abstract

Functional verification is one of the dominant costs in modern chip development, yet most LLM-for-EDA work stops at artifact generation — Verilog or assertions evaluated on small, open-source designs — rather than closing the loop of executing, triaging, and iterating on real industrial IP. This talk presents a case study of a fully autonomous agentic verification workflow built with NVIDIA around Cadence ChipStack AI SuperAgent, orchestrated by Codex (GPT-5.5) inside a sandboxed NVIDIA OpenShell runtime that drives Cadence Xcelium simulation and Cadence Jasper formal verification. From only high-level natural-language objectives, the system builds design mental models, plans and generates SystemVerilog testbenches and formal properties, runs them against designs, triages failures, and persists auditable artifacts at every stage. We evaluate it on two industrially relevant proof points across seven metric axes that mirror DV sign-off. We share central findings, directional productivity evidence, the failure modes that matter most, and what it takes to actually trust an autonomous verification agent.

Bio

Sandesh Adhikary is a Senior Principal Software Engineer at Cadence Design Systems, where he builds LLM-based agents for chip design with a focus on reinforcement learning for tool usage and domain adaptation. He holds a PhD and MS in Computer Science from the University of Washington and a BS in Physics from Reed College, with research focused on incorporating geometric structural priors in machine learning — from metric-informed RL to quantum-inspired probabilistic modeling.

Neil Ashton is the Distinguished Engineer & Product Architect for CAE at NVIDIA. Fellow of the Institution of Mechanical Engineers. Previously: WW Tech Lead for CAE at AWS, Senior Researcher at Oxford University, and engineering contributor for Formula 1 and British Cycling.

CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research

Abstract

We introduce CHIA, an open-source hardware/software co-design framework for agile and principled research on the application of AI to co-design (https://chialoops.ai, OpenReview, June 2026: https://openreview.net/pdf?id=lLxEUReWHG). CHIA treats the productive construction and scalable deployment of the co-design flow itself as a first-class objective. CHIA transforms agentic AI-driven hardware and software design flows into CHIA loops: directed cyclic graphs whose nodes execute various system-on-chip design tools, microarchitectural simulators, software build systems, AI models, evolutionary coding agents, and more. The CHIA library provides node implementations for many popular tools, including Chipyard, gem5, ChampSim, FireSim, Hammer (thus several commercial ASIC CAD tools), Vivado, AlphaEvolve, AdaEvolve, and many others. We will discuss several case studies (with heavy verification and validation, e.g. 25+ trillion instructions of SPEC-Ref) to show CHIA's capabilities and are excited to see what the community does with CHIA!

Bio

Angela Cui is a first-year Ph.D. student at UC Berkeley, advised by Sagar Karandikar. She is an NSF GRFP Fellow. She is a co-creator of CHIA (https://chialoops.ai).

Ferran Hermida-Rivera is a first-year Ph.D. student at UC Berkeley, advised by Sagar Karandikar. He is a co-creator of CHIA.

Jack Toubes is a first-year Ph.D. student at UC Berkeley, advised by Sagar Karandikar. He is an NSF GRFP Fellow and he is a co-creator of CHIA.

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