Invited Talks

Test input generators are a popular tool for assuring the quality of software and hardware. A test input generator is a non-deterministic function which can be used to send a large number of randomized inputs for a particular test driver. However, when the test driver requires strict validity constraints on the inputs, completely random input generation fails to generate enough valid inputs. Existing approaches to solving this problem rely on whitebox or greybox information collected by instrumenting the input generator and/or test driver. However, collecting such information reduces the speed at which tests can be executed. This talk discusses a blackbox approach for generating valid test inputs, based on reinforcement learning (RL). First, I will frame how the problem can be viewed as an RL problem. Then, I will present our solution, RLCheck, that uses a tabular, on-policy RL approach to guide the test input generator. I will outline the key points of success of RLCheck on our software benchmarks---in particular, the choice of a good level of state/action abstraction. I will also present results for a deep Q-learning prototype of RLCheck, which utilizes curiosity to increase the diversity of valid inputs generated --- highlighting the strength and weaknesses of this approach.

Abstract

As deep learning continues to revolutionize a variety of domains, training of Deep Neural Networks (DNNs) is emerging as a prominent workload in data centers. Data parallel DNN training is commonly employed for scalability. However, the relationship between communication and computation, a key factor that affects the DNN training throughput, is often overlooked in this network- and compute-intensive workload. In this talk, I will cast light on the communication-computation interdependencies that are critical for DNN training acceleration, and present two systems that significantly improve the training performance by leveraging this understanding. I will first discuss the communication paradigms, Parameter Server and AllReduce, and examine scalability challenges in each of them. I will then present TicTac, a system that optimizes training throughput by up to 37% through computation-aware parameter transfer scheduling in Parameter Servers. Finally, I will elaborate on the need for a different approach to tackle the same problem under AllReduce. I will introduce our system, Caramel, which improves training throughput under AllReduce by up to 3.62x using computation scheduling to achieve better communication-computation overlap.

Abstract

Deploying deep neural networks (DNN) on embedded systems for computer vision has been challenging due to limited compute resources and strict energy budgets. In this talk, I will present an algorithm-hardware co-design approach we adopt to accelerate DNN models on embedded FPGAs for computer vision tasks, such as image classification and object detection. In our DNN designs, we employ novel operators, such as the shift operation and the deformable convolution. We modify both the models and the operations to make them more compatible with FPGA architectures. For image classification, we developed DiracDeltaNet, which is a ConvNet with only 1x1 convolutions with spatial convolutions being replaced by more efficient shift operations. For object detection, we designed an efficient anchor-free DNN model and codesigned the deformable convolution operation. In both works, we achieve real-time inference with competitive accuracy on the target embedded FPGA. We use High-level Synthesis (HLS) to generate hardware for the FPGA accelerators, which greatly reduces our design time. Since the quality of results from HLS is greatly impacted by the optimization decisions made in the frontend compiler, we apply machine learning to drive the optimization decisions. More specifically, we applied deep reinforcement learning to address the phase-ordering problem in the HLS compiler and show that RL can significantly improve the circuit performance compared to using the -O3 compiler flag, and achieves competitive results with state-of-the-art solutions, while requiring fewer samples.