Keynote Talks
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Abstract
The hardware design space is high-dimensional and discrete. Systematic and efficient exploration of this space has been a significant challenge. Central to this problem is the intractable search complexity that grows exponentially with the design choices and the discrete nature of the search space. This work investigates the feasibility of learning a meaningful low-dimensional continuous representation for hardware designs to reduce such complexity and facilitate the search process. We devise a variational autoencoder (VAE)-based design space exploration framework called VAESA, to encode the hardware design space in a compact and continuous representation. We show that black-box and gradient-based design space exploration algorithms can be applied to the latent space, and design points optimized in the latent space can be reconstructed to high-performance realistic hardware designs. Our experiments show that performing the design space search on the latent space consistently leads to the optimal design point under a fixed number of samples. In addition, the latent space can improve the sample efficiency of the original algorithm by 6.8x.
Bio
Qijing Huang is a research scientist at NVIDIA Research. Her research interests are in hardware accelerator, HLS-based design flow, and ML/optimization-assisted compiler and CAD flow. Previously, She earned her PhD in Computer Science at UC Berkeley and has worked on building efficient FPGA accelerators for emerging ML applications, HLS-based hardware/software flow, and ML-assisted HLS and CAD flow. Her thesis focuses on novel design and scheduling techniques for accelerating machine learning algorithms on heterogeneous architecture. Prior to UC Berkeley, She received her B.A.Sc. from the University of Toronto.
Learning Architecture and Mapping Space for DNN Accelerators
Abstract
Custom architecture design is an exciting avenue for architects to come up with designed tailored for specific workloads achieving both high performance and energy efficiency. The vastness of the design spaces however, limit human designers’ ability to hunt down globally optimal configurations in most cases. However, given this complexity and the problem being inherently data driven in nature, it is a perfect candidate operation for ML based design problem. In this talk I will speak about our recent work on systematically exploring the DNN accelerator design and mapping space to understand the feasibility of learning the spaces. This talk will also cover some of the experiments we performed to construct and train an ANN model to learn these spaces and then predict the optimal architecture and mapping configurations when queried with workload parameters and design constraints.
Bio
Ananda Samajdar is a Research Staff Member in the AI and architectures group at IBM TJ Watson Research lab. Anand obtained his PhD from Georgia Tech in 2021. Anand’s research interest includes designing custom architectures for efficient and deep learning systems and continuous learning systems. He has been the author of several papers in top-tier computer architecture conferences. A couple of his papers are honorable mentions in the IEEE MICRO Top picks 2019, and one was awarded the best paper award at HPCA2020.