Keynote Talks

Abstract

While much attention and venture investment has focused on Neural Net Accelerator chips and architectures, the software stack that sits above these devices has not gotten comparable investment or consideration. This is a mistake! In this talk I’ll walk through a few applications in computer vision, speech, and natural language, and I will demonstrate how proper orchestration of application constraints, NN model architecture, model optimization, frameworks and libraries, and HW/SW co-design can give 10-100x improvements in latency over straightforward implementations.

Abstract

While generative models for code completion are currently popular, code construction is just a small part of software development. Instead, code maintenance spans a much larger proportion of the development activity. In this talk, I will discuss deep learning models and training methods that find and fix seemingly simple but hard-to-find bugs. Specifically, they target bugs where there is a mismatch between the (latent) intent of the developer and source code. This requires models that reason over highly-structured data and code's formal semantics. Here, structured deep learning models achieve state-of-the-art performance and the trained models find previously unknown bugs in open-source projects on GitHub. I will conclude by discussing open challenges and opportunities in this area.

Abstract

In this talk, we start from the observation that investments in special HW for Neural Network is sky rocketing, and that to leverage all these new capabilities for database, classical ML, and other workloads we would incur a massive N x M engineering effort. We then focus on tensor computations as a key API supported by many vendors and NN runtime platforms, and show that we can translate (in less than 10k lines of python code) SQL queries, classical ML inference and graph algorithms to tensor computations. The results are surprisingly promising, allowing us to match and outperform both CPU and custom CPU state of the art systems. We also demonstrate unparalleled portability, running natively on CPUs, GPUs, APUs, TPUs, and even browsers and mobiles environments. We conclude by showcasing other interesting side advantages of this approach that blend SQL+ML in interesting new ways.

Abstract

We present Design2Vec, a deep representation learning based approach to learn semantics of hardware designs at the Register Transfer Level (RTL). Design2Vec creates an abstraction of the RTL design state space using a combination of representations based on the design graph and source code. These neural network generated design abstractions can effectively be used in different phases of chip design. This is the first work to learn a continuous representation of hardware designs that can be used for a variety of different applications like design verification, high level synthesis, efficient simulation, design understanding etc.

Here, we apply Design2Vec on two design verification tasks. Design verification is considered as the biggest bottleneck in chip design, due to the inherent theoretical complexity of this problem resulting in state space explosion. Practical industrial methods for design verification are best efforts that take unacceptably long and drain resources. We trained Design2Vec on two tasks- as a proxy simulator and for test generation. In both these tasks, Design2Vec performs much better than the state of practice in the DV industry. It also performs orders of magnitude better than blackbox ML approaches. Design2Vec can scale to real designs like the TPU, and can achieve coverage that is hard to achieve through current industrial DV approaches.

Abstract

Developing an optimizing compiler is a highly skilled and arduous process, and there is inevitably a software delay whenever a new processor is designed. It often takes several generations of a compiler to start to effectively exploit the processors' potential, by which time a new processor appears, and the process starts again. This never-ending game of catch-up means that we rarely fully exploit a shipped processor, which inevitably delays time to market. As the pace of hardware evolution accelerates, this problem increases. This talk will look at research undertaken in using machine learning to automate designing compiler optimization heuristics and will outline some of the challenges ahead.