ldps.giee.ntu - Digital Switching Noise

Digital Switching Noise, 3-D Integrated Circuits

On this page, we have included a list of our research results related to digital switching noise and 3-D integrated circuits. Among them, the work of [2-5] was a nominee of the best paper award in the 2009 IEEE/ACM International Conference on Computer-Aided Design. The work was to propose a compact circuit model for predicting the thermal behaviors of substrates and micro-fluidic-channels inside a 3-D integrated circuit. In the later journal version, a 3,300X speed-up can be achieved when compared to the conventional numerical approach.

Digital Switching Noise in 2-D/3-D ICs

[1-1] Y. H. Lin, J. Chou, Y. C. Lu, T. L. Wu, and H. S. Chen, "Chip-package-board co-design - a DDR3 system design example from circuit designers’ perspective," in 2008 Electrical Design of Advanced Packaging and Systems Symposium, 2008, pp. 27-30. [1-2] H. H. Chuang, W. D. Guo, Y. H. Lin, H. S. Chen, Y. C. Lu, Y. S. Cheng, M. Z. Hong, C. H. Yu, W. C. Cheng, Y. P. Chou, C. J. Chang, J. Ku, T. L. Wu, and R. B. Wu, "Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis," IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 2, pp. 381-391, May 2010.[1-3] Y. C. Lu, C. H. Li, C. Y. Kuo, and T. Y. Wu, "Power distribution system," United States Patent, no. 7,952,229 B2, May 2011.[1-4] Y. C. Lu, C. H. Li, C. Y. Kuo, and T. Y. Wu, "Layout of a reference generating system," United States Patent, no. 8,148,971 B2, Apr. 2012.[1-5] Y. J. Chang, T. Y. Zheng, H. H. Chuang, C. D. Wang, P. S. Chen, T. Y. Kuo, C. J. Zhan, S. H. Wu, W. C. Lo, Y. C. Lu, Y. P. Chiou, and T. L. Wu, "Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer," in 2012 IEEE 62nd Electronic Components and Technology Conference, 2012, pp. 1934-1938.[1-6] Y. J. Chang, H. H. Chuang, Y. C. Lu, Y. P. Chiou, T. L. Wu, P. S. Chen, S. H. Wu, T. Y. Kuo, C. J. Zhan, and T. L. Wu, "Novel crosstalk modeling for multiple Through-Silicon-Vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design," in 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, 2012, pp. 232-235.[1-7] Y. C. Tseng, C. B. Chang, C. K. Tang, C. H. Cheng, Y. C. Lu, K. Y. Lin, T. L. Wu, and R. B. Wu, "Design considerations for radio frequency 3DICs," in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, 2012, pp. 197-200.[1-8] C. K. Shen, Y. C. Lu, Y. P. Chiou, T. Y. Cheng, and T. L. Wu, "Power distribution network modeling for 3-D ICs with TSV arrays," in 2013 18th Asia and South Pacific Design Automation Conference, 2013, pp. 17-22.[1-9] C. D. Wang, Y. J. Chang, Y. C. Lu, P. S. Chen, W. C. Lo, Y. P. Chiou, and T. L. Wu, "ABF-Based TSV Arrays with Improved Signal Integrity on 3-D IC/Interposers: Equivalent Models and Experiments," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 10, pp. 1744-1753, Oct. 2013.[1-10] C. H. Cheng, T. Y. Cheng, C. H. Du, Y. C. Lu, Y. P. Chiou, S. Liu, and T. L. Wu, "An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks with an Emphasis on Coupling Effect," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 6, pp. 1062-1070, June 2014.[1-11] Y. A. Hsu, C. H. Cheng, Y. C. Lu, and T. L. Wu, "An Accurate and Fast Substrate Noise Prediction Method with Octagonal TSV Model for 3-D ICs," IEEE Transactions on Electromagnetic Compatibility, vol. 59, no. 5, pp. 1549-1557, May 2017.[1-12] C. K. Shen, Y. C. Lu, Y. P. Chiou, H. H. Hsieh, M. H. Tsai, S. Liu, and T. L. Wu, "EGB-Based Grid-Type PDN on Interposer for SSN Mitigation in Mixed-Signal System-in-Package," IEEE Microwave and Wireless Components Letters, vol. 27, no. 12, pp. 1053-1055, Dec. 2017.[1-13] C. C. Chou, S. S. Weng, Y. C. Lu, and T. L. Wu, "EMI-reduction coding based on 8b/10b," IEEE Transactions on Electromagnetic Compatibility, 2018. (To appear)

Thermal and Delay Issues in 3-D ICs

[2-1] Y. C. Lu, "3D technology based circuit and architecture design," in 2009 International Conference on Communications, Circuits and Systems, 2009, pp. 1124-1128.[2-2] H. Mizunuma, C. L. Yang, and Y. C. Lu, "Thermal modeling for 3D-ICs with integrated microchannel cooling," in 2009 IEEE/ACM International Conference on Computer-Aided Design, 2009, pp. 256-263.[2-3] Y. R. Huang, J. H. Pan, and Y. C. Lu, "Thermal-aware router-sharing architecture for 3D Network-on-Chip designs," in 2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010, pp. 1087-1090.[2-4] C. H. Lin, Y. C. Lu, C. K. Tang, and K. Y. Tsai, "The effect of NBTI on 3D integrated circuits," in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, 2012, pp. 201-204.[2-5] H. Mizunuma, Y. C. Lu, and C. L. Yang, "Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 9, pp. 1293-1306, Sep. 2011.[2-6] H. Mizunuma, Y. C. Lu, and C. L. Yang, "Thermal coupling aware task migration using neighboring core search for many-core systems," in 2013 International Symposium on VLSI Design, Automation, and Test, 2013, pp. 1-4.[2-7] P. S. Lin, Y. J. Chen, C. L. Yang, and Y. C. Lu, "Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs," in 2013 International Symposium on Low Power Electronics and Design, 2013, pp. 304-304.[2-8] C. J. Shih, S. A. Hsieh, Y. C. Lu, J. C. M. Li, T. L. Wu, and K. Chakrabarty, "Test Generation of Path Delay Faults Induced by Defects in Power TSV," in 2013 22nd Asian Test Symposium, 2013, pp. 43-48.[2-9] C. Y. Kuo, C. J. Shih, Y. C. Lu, J. C. M. Li, and K. Chakrabarty, "Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 667-674, Mar. 2014.[2-10] Y. J. Chen, C. L. Yang, P. S. Lin, and Y. C. Lu, "Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs," in 2015 Conference on Research in Adaptive and Convergent Systems, 2015, pp. 430-436.[2-11] Y. A. Hsu, C. H. Cheng, T. L. Wu, and Y. C. Lu, "A prediction method of heat generation in the silicon substrate for 3-D ICs," in 2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems, 2015, pp. 89-91. [2-12] Y. J. Chen, C. L. Yang, P. S. Lin, and Y. C. Lu, “Opportunities of synergistically adjusting voltage-frequency levels of cores and DRAMs in CMPs with 3d-stacked DRAMs for efficient thermal control,” ACM SIGAPP Applied Computing Review, vol. 16, no. 1, pp. 26-35, Mar. 2016.

Earlier Work

[3-1] Y. C. Lu, K. Banerjee, M. Celik, and R. W. Dutton, "A fast analytical technique for estimating the bounds of on-chip clock wire inductance," in 2001 IEEE Custom Integrated Circuits Conference, 2001, pp. 241-244.[3-2] Y. C. Lu, M. Celik, T. Young, and L. T. Pileggi, "Minimax on-chip inductance models and delay metrics," in 2001 ACM 38th Design Automation Conference, 2001, pp. 341-346.[3-3] H. Lan, Y. C. Lu, N. Nakano, and R. W. Dutton, “Efficient techniques for reducing complexity of substrate models in mixed-signal ICs,” in 2003 11th Workshop on Synthesis and Signal Integration of Mixed Information Technologies, 2003, pp. 83-88.[3-4] G. Veronis, Y. C. Lu, and R. W. Dutton, "Modeling of wave behavior of substrate noise coupling for mixed-signal IC design," in 2004 5th International Symposium on Quality Electronic Design, 2004, pp. 303-308.[3-5] Y. C. Lu, J. W. Kim, N. Nakano, D. Colleran, P. Yue, and R. W. Dutton, “Realization of digital noise emulator for characterization of systems exposed to substrate noise,” in 2004 12th Workshop on Synthesis and Signal Integration of Mixed Information Technologies, 2004, pp. 196-203.[3-6] Y. C. Lu, “Digital noise emulator for characterization of phase-locked-loop systems exposed to substrate noise,” Ph.D. Dissertation, Stanford University (ProQuest, ISBN: 0496135333), Jan. 2005.[3-7] J. W. Kim, Y. C. Lu, and R. W. Dutton, "Modeling and simulation of jitter in phase-locked loops due to substrate noise," in 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005, pp. 25-30.[3-8] M. Lin, A. El Gamal, Y. C. Lu, and S. Wong, "Performance benefits of monolithically stacked 3D-FPGA," in 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006, pp. 113-122.[3-9] T. W. Chen, J. H. Chun, Y. C. Lu, R. Navid, W. Wang, and R. W. Dutton, "Thermal modeling and device noise properties of 3D-SOI Technology," in 2007 IEEE International SOI Conference, 2007, pp. 89-90.[3-10] M. Lin, A. El Gamal, Y. C. Lu, and S. Wong, "Performance Benefits of Monolithically Stacked 3-D FPGA," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 216-229, Feb. 2007.[3-11] C. Iorga, Y. C. Lu, and R. W. Dutton, "A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications," IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 6, pp. 2330-2337, Dec. 2007.[3-12] T. W. Chen, J. H. Chun, Y. C. Lu, R. Navid, W. Wang, C. L. Chen, and R. W. Dutton, "Thermal Modeling and Device Noise Properties of Three-Dimensional-SOI Technology," IEEE Transactions on Electron Devices, vol. 56, no. 4, pp. 656-664, Apr. 2009.

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