Journal Papers

[J1] Y.-H. Lin and Y.-C. Lu, “Low-light enhancement using a plug-and-play Retinex model with shrink-

age mapping for illumination estimation,” IEEE Transactions on Image Processing, vol. 31, pp.

4897–4908, 2022.

[J2] Y.-M. Yeh and Y.-C. Lu, “MSRCall: a multi-scale deep neural network to basecall Oxford

Nanopore sequences,” Bioinformatics, vol. 38, no. 16, pp. 3877–3884, 2022.

[J3] C.-H. Yang, Y.-H. Lin, and Y.-C. Lu, “A variation-based nighttime image dehazing flow with

a physically valid illumination estimator and a luminance-guided coloring model,” IEEE Access,

vol. 10, pp. 50 153–50 166, 2022.

[J4] S. Yuan, G. Wu, Y.-C. Li, Y.-C. Lu, and K.-C. Li, “GPU accelerated liquid association GALA,”

Statistics and Its Interface, vol. 13, no. 1, pp. 119–125, 2020.

[J5] Y.-C. Li and Y.-C. Lu, “BLASTP-ACC: Parallel architecture and hardware accelerator design

for BLAST-based protein sequence alignment,” IEEE Transactions on Biomedical Circuits and

Systems, vol. 13, no. 6, pp. 1771–1782, 2019.

[J6] C.-C. Chou, S.-S. Weng, Y.-C. Lu, and T.-L. Wu, “EMI-reduction coding based on 8b/10b,” IEEE

Transactions on Electromagnetic Compatibility, vol. 61, no. 4, pp. 1007–1014, 2018.

[J7] C.-C. Yu, P.-C. Lin, Y.-C. Lu, and C. C.-P. Chen, “Cost-effective and channel-scalable hard-

ware decoders for multiple electron-beam direct-write systems,” Journal of Micro/Nanolithography,

MEMS, and MOEMS, vol. 17, no. 3, p. 031202, 2018.

[J8] C.-K. Shen, Y.-C. Lu, Y.-P. Chiou, H.-H. Hsieh, M.-H. Tsai, S. Liu, and T.-L. Wu, “EBG-based

grid-type PDN on interposer for SSN mitigation in mixed-signal system-in-package,” IEEE Mi-

crowave and Wireless Components Letters, vol. 27, no. 12, pp. 1053–1055, 2017.

[J9] Y.-A. Hsu, C.-H. Cheng, Y.-C. Lu, and T.-L. Wu, “An accurate and fast substrate noise pre-

diction method with octagonal TSV model for 3-D ICs,” IEEE Transactions on Electromagnetic

Compatibility, vol. 59, no. 5, pp. 1549–1557, 2017.

[J10] C.-K. Tang, M.-S. Su, and Y.-C. Lu, “Efficient layout data compression algorithm and its low-

complexity, high-performance hardware decoder implementation for multiple electron-beam direct-

write systems,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 14, no. 3, p. 031212,

2015.

[J11] C.-H. Cheng, T.-Y. Cheng, C.-H. Du, Y.-C. Lu, Y.-P. Chiou, S. Liu, and T.-L. Wu, “An equation-

based circuit model and its generation tool for 3-D IC power delivery networks with an emphasis

on coupling effect,” IEEE Transactions on Components, Packaging and Manufacturing Technology,

vol. 4, no. 6, pp. 1062–1070, 2014.

[J12] C.-Y. Kuo, C.-J. Shih, Y.-C. Lu, J. C.-M. Li, and K. Chakrabarty, “Testing of TSV-induced small

delay faults for 3-D integrated circuits,” IEEE Transactions on Very Large Scale Integration (VLSI)

Systems, vol. 22, no. 3, pp. 667–674, 2013.

[J13] C.-D. Wang, Y.-J. Chang, Y.-C. Lu, P.-S. Chen, W.-C. Lo, Y.-P. Chiou, and T.-L. Wu, “ABF-based

TSV arrays with improved signal integrity on 3-D IC/interposers: Equivalent models and exper-

iments,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3,

no. 10, pp. 1744–1753, 2013.

[J14] C.-K. Tang, M.-S. Su, and Y.-C. Lu, “LineDiff Entropy: lossless layout data compression scheme

for maskless lithography systems,” IEEE Signal Processing Letters, vol. 20, no. 7, pp. 645–648,

2013.

[J15] H. Mizunuma, Y.-C. Lu, and C.-L. Yang, “Thermal modeling and analysis for 3-D ICs with inte-

grated microchannel cooling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, vol. 30, no. 9, pp. 1293–1306, 2011.

[J16] P. C. Ng, S.-W. Chien, B.-S. Chang, K.-Y. Tsai, Y.-C. Lu, J.-H. Li, and A. C. Chen, “Impact of

process-effect correction strategies on variability of critical dimension and electrical characteristics

in extreme ultraviolet lithography,” Japanese Journal of Applied Physics, vol. 50, no. 6, p. 06GB07,

2011.

[J17] H.-H. Chuang, W.-D. Guo, Y.-H. Lin, H.-S. Chen, Y.-C. Lu, Y.-S. Cheng, M.-Z. Hong, C.-H. Yu,

W.-C. Cheng, Y.-P. Chou, C.-J. Chang, J. Ku, T.-L. Wu, and R.-B. Wu, “Signal/power integrity

modeling of high-speed memory modules using chip-package-board coanalysis,” IEEE Transactions

on Electromagnetic Compatibility, vol. 52, no. 2, pp. 381–391, 2010.

[J18] T. W. Chen, J.-H. Chun, Y.-C. Lu, R. Navid, W. Wang, C.-L. Chen, and R. W. Dutton, “Thermal

modeling and device noise properties of three-dimensional-SOI technology,” IEEE Transactions on

Electron Devices, vol. 56, no. 4, pp. 656–664, 2009.

[J19] C. Iorga, Y.-C. Lu, and R. W. Dutton, “A built-in technique for measuring substrate and power-

supply digital switching noise using PMOS-based differential sensors and a waveform sampler in

system-on-chip applications,” IEEE Transactions on Instrumentation and Measurement, vol. 56,

no. 6, pp. 2330–2337, 2007.

[J20] M. Lin, A. El Gamal, Y.-C. Lu, and S. Wong, “Performance benefits of monolithically stacked

3-D FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

vol. 26, no. 2, pp. 216–229, 2007.

Conference Papers

[C1] H.-Y. Shu, Y.-H. Lin, and Y.-C. Lu, “Deep plug-and-play nighttime non-blind deblurring with

saturated pixel handling schemes,” in 2024 IEEE/CVF Winter Conference on Applications of

Computer Vision. IEEE, 2024, pp. 1527–1535.

[C2] C.-H. Hsu, Y.-H. Lin, Y.-P. Lin, and Y.-C. Lu, “A multiframe super-resolution pipeline for sub-

image-typed light field data,” in 2022 Asia-Pacific Signal and Information Processing Association

Annual Summit and Conference. IEEE, 2022, pp. 1614–1619.

[C3] Y.-Y. Tseng, Y.-L. Wu, Y.-P. Lin, Y.-M. Yeh, and Y.-C. Lu, “Design of a power efficient accelerator

for reconstructing videos from Gaussian mixture model data,” in IEEE Region 10 Conference.

IEEE, 2022, pp. 1–4.

[C4] C.-Y. Chen, S.-H. Huang, and Y.-C. Lu, “A hardware accelerator for long sequence alignment

with the bit-vector scoring scheme and divide-and-conquer traceback,” in 2022 IEEE Biomedical

Circuits and Systems Conference. IEEE, 2022, pp. 467–471.

[C5] H.-W. Liu, Z.-W. Shen, Y.-M. Yeh, and Y.-C. Lu, “A nucleotide-position-based data format for

fast variant calling and its hardware analyzer design,” in 2022 IEEE Biomedical Circuits and

Systems Conference. IEEE, 2022, pp. 529–533.

[C6] S.-W. Hsieh, C.-H. Yang, and Y.-C. Lu, “Shadow removal through learning-based region matching

and mapping function optimization,” in 2022 IEEE International Conference on Multimedia and

Expo. IEEE, 2022, pp. 1–6.

[C7] S.-S. Weng, Y.-M. Yeh, Y.-C. Li, and Y.-C. Lu, “An alignment-based hardware accelerator for

rapid prediction of RNA secondary structures,” in 2022 IEEE International Symposium on Circuits

and Systems. IEEE, 2022, pp. 2700–2704.

[C8] B.-F. Chen, Y.-M. Yeh, and Y.-C. Lu, “CF-Net: Complementary fusion network for rotation

invariant point cloud completion,” in 2022 IEEE International Conference on Acoustics, Speech

and Signal Processing. IEEE, 2022, pp. 2275–2279.

[C9] Y.-P. Lin, Y.-M. Yeh, Y.-C. Chou, and Y.-C. Lu, “Attention EdgeConv for 3D point cloud classi-

fication,” in 2021 Asia-Pacific Signal and Information Processing Association Annual Summit and

Conference. IEEE, 2021, pp. 2018–2022.

[C10] Y.-C. Chou, Y.-P. Lin, Y.-M. Yeh, and Y.-C. Lu, “3D-GFE: A three-dimensional geometric-feature

extractor for point cloud data,” in 2021 Asia-Pacific Signal and Information Processing Association

Annual Summit and Conference. IEEE, 2021, pp. 2013–2017.

[C11] F.-T. Hsiao, Y.-H. Lin, and Y.-C. Lu, “Using regularity unit as guidance for summarization-

based image resizing,” in 2021 International Conference on Visual Communications and Image

Processing. IEEE, 2021, pp. 1–5.

[C12] S.-J. Huang, Y.-H. Lin, C.-H. Weng, and Y.-C. Lu, “A real time video stabilizer based on feature

trajectories and global mesh warping,” in 2021 IEEE Asia Pacific Conference on Circuit and

Systems. IEEE, 2021, pp. 69–72.

[C13] W.-Y. Duh, Y.-H. Lin, and Y.-C. Lu, “RGB-NIR demosaicking using a two-phase primal-dual

algorithm with a Laplacian guided image filter prior,” in 2021 IEEE International Conference on

Consumer Electronics-Asia. IEEE, 2021, pp. 1–4.

[C14] J.-P. Wu, Y.-C. Lin, Y.-W. Wu, S.-W. Hsieh, C.-H. Tai, and Y.-C. Lu, “A memory-efficient acceler-

ator for DNA sequence alignment with two-piece affine gap tracebacks,” in 2021 IEEE International

Symposium on Circuits and Systems. IEEE, 2021, pp. 1–4.

[C15] C.-C. Yu, Y. H. Hu, Y.-C. Lu, and C. C.-P. Chen, “Power reduction of a set-associative instruction

cache using a dynamic early tag lookup,” in 2021 Design, Automation Test in Europe Conference

Exhibition. IEEE, 2021, pp. 1799–1802.

[C16] C.-Y. Liou, C.-Y. Chuang, C.-H. Huang, and Y.-C. Lu, “HDR deghosting using motion-

registration-free fusion in the luminance gradient domain,” in 2020 IEEE International Conference

on Visual Communications and Image Processing. IEEE, 2020, pp. 499–502.

[C17] C.-H. Ho, Y.-H. Lin, J. S.-I. Hu, and Y.-C. Lu, “Design and implementation of a hand-held lensless

light field camera,” in 2020 IEEE International Conference on Consumer Electronics-Asia. IEEE,

2020, pp. 1–4, Best Paper Award.

[C18] Y.-C. Li, M.-J. Lin, X.-X. Huang, C.-Y. Chen, and Y.-C. Lu, “Comprehensive study of keywords

for sequence-based automatic annotation of protein functions,” in 2020 IEEE 20th International

Conference on Bioinformatics and Bioengineering. IEEE, 2020, pp. 23–28.

[C19] C.-H. Huang and Y.-C. Lu, “An image deblurring processor for chromatic aberration based on

the primal-dual algorithm with cross-channel prior,” in 2020 IEEE International Symposium on

Circuits and Systems. IEEE, 2020, pp. 1–5.

[C20] C.-Y. Yang, Y.-M. Yeh, and Y.-C. Lu, “Hardware architecture and implementation of clustered

tensor approximation for multi-dimensional visual data,” in 2020 International Symposium on

VLSI Design, Automation and Test. IEEE, 2020, pp. 1–3.

[C21] M.-H. Chen, M.-J. Lin, Y.-C. Li, and Y.-C. Lu, “Banded Pair-HMM algorithm for DNA variant

calling and its hardware accelerator design,” in 2019 IEEE 19th International Conference on

Bioinformatics and Bioengineering. IEEE, 2019, pp. 563–566.

[C22] M.-J. Lin, Y.-C. Li, and Y.-C. Lu, “Hardware accelerator design for dynamic-programming-based

protein sequence alignment with affine gap tracebacks,” in 2019 IEEE Biomedical Circuits and

Systems Conference. IEEE, 2019, pp. 1–4.

[C23] Y.-M. Yeh, J. S.-I. Hu, Y.-Y. Lin, and Y.-C. Lu, “Compressing DNN parameters for model loading

time reduction,” in 2019 IEEE International Conference on Consumer Electronics-Asia. IEEE,

2019, pp. 78–79.

[C24] Y.-Y. Lin, Y.-H. Lin, M.-J. Lin, Y.-M. Yeh, and Y.-C. Lu, “A depth-assisted deblurring flow using

dual cameras with different exposure times,” in 2019 IEEE International Conference on Consumer

Electronics-Asia. IEEE, 2019, pp. 9–10, Best Paper Award.

[C25] M.-R. Chen, H.-W. Liu, Y.-H. Lin, and Y.-C. Lu, “A special-purpose processor for FFT-based

digital refocusing using 4-D light field data,” in 2019 IEEE International Symposium on Circuits

and Systems. IEEE, 2019, pp. 1–5.

[C26] C.-F. Chiang, Y.-M. Yeh, C.-Y. Yang, and Y.-C. Lu, “Colorization of high-frame-rate monochrome

videos using synchronized low-frame-rate color data,” in International Workshop on Computational

Color Imaging. Springer, Cham, 2019, pp. 276–285.

[C27] C.-A. Wang, S.-J. Huang, Y.-C. Li, and Y.-C. Lu, “An FPGA-based liquid association calculator

for genome-wide co-expression analysis,” in 2018 IEEE 23rd International Conference on Digital

Signal Processing. IEEE, 2018, pp. 1–4.

[C28] R.-T. Chien, Y.-L. Liao, C.-A. Wang, Y.-C. Li, and Y.-C. Lu, “Three-dimensional dynamic pro-

gramming accelerator for multiple sequence alignment,” in 2018 IEEE Nordic Circuits and Systems

Conference. IEEE, 2018, pp. 1–5.

[C29] S.-W. Hsieh, Y.-C. Yang, C.-M. Yeh, S.-J. Huang, and Y.-C. Lu, “Subpixel-level-accurate algo-

rithm for removing double-layered reflections from a single image,” in 2018 25th IEEE International

Conference on Image Processing. IEEE, 2018, pp. 395–399.

[C30] Y.-L. Liao, Y.-C. Li, N.-C. Chen, and Y.-C. Lu, “Adaptively banded Smith-Waterman algorithm

for long reads and its hardware accelerator,” in 2018 IEEE 29th International Conference on

Application-specific Systems, Architectures and Processors. IEEE, 2018, pp. 1–9.

[C31] P.-H. Hsu, Y.-M. Yeh, C.-M. Yeh, and Y.-C. Lu, “A high dynamic range light field camera and its

built-in data processor design,” in 2018 IEEE International Symposium on Circuits and Systems.

IEEE, 2018, pp. 1–5.

[C32] M.-J. Lin, C.-Y. Chang, Y.-C. Li, N.-C. Chen, and Y.-C. Lu, “A hybrid flow for multiple sequence

alignment with a BLASTn based pairwise alignment processor,” in 2018 IEEE International Sym-

posium on Circuits and Systems. IEEE, 2018, pp. 1–5.

[C33] Y.-F. Shih, Y.-M. Yeh, Y.-Y. Lin, M.-F. Weng, Y.-C. Lu, and Y.-Y. Chuang, “Deep co-occurrence

feature learning for visual object recognition,” in 2017 IEEE Conference on Computer Vision and

Pattern Recognition, 2017, pp. 4123–4132.

[C34] C.-W. Chang, M.-H. Chen, K.-C. Chen, C.-M. Yeh, and Y.-C. Lu, “Mask design for pinhole-array-

based hand-held light field cameras with applications in depth estimation,” in 2016 Asia-Pacific

Signal and Information Processing Association Annual Summit and Conference. IEEE, 2016, pp.

1–4.

[C35] C.-Y. Chang, Y.-C. Li, N.-C. Chen, X.-X. Huang, and Y.-C. Lu, “A special processor design for

nucleotide basic local alignment search tool with a new banded two-hit method,” in 2016 IEEE

Nordic Circuits and Systems Conference. IEEE, 2016, pp. 1–5.

[C36] C.-S. Liu, N.-C. Chen, Y.-C. Li, and Y.-C. Lu, “An FPGA-based quality filter for de novo sequence

assembly pipeline,” in 2016 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2016,

pp. 139–142.

[C37] X.-X. Huang, C.-H. Ho, Y.-C. Li, N.-C. Chen, and Y.-C. Lu, “Step shift: A fast image segmentation

algorithm and its hardware implementation for next-generation sequencing fluorescence data,” in

2016 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2016, pp. 202–205.

[C38] L. Xiao, X.-X. Huang, and Y.-C. Lu, “Non-photorealistic rendering from real video sequences

with discontinuity reduction using fast video segmentation,” in 2016 International SoC Design

Conference. IEEE, 2016, pp. 327–328.

[C39] Y.-M. Yeh, C.-M. Yeh, Y.-Y. Tseng, and Y.-C. Lu, “An orthogonal matching pursuit processor for

sparse-representation-based light field data compression,” in 2016 IEEE 5th Global Conference on

Consumer Electronics. IEEE, 2016, pp. 1–2.

[C40] Y.-H. Kao, S.-J. Huang, and Y.-C. Lu, “An iterative re-weighted least squares processor design

for deblurring parabolic camera images,” in 2016 IEEE 5th Global Conference on Consumer Elec-

tronics. IEEE, 2016, pp. 1–2.

[C41] Y.-H. Chen, N.-C. Chen, Y.-H. Kao, Y.-C. Li, and Y.-C. Lu, “Queue-based segmentation algorithm

for refining depth maps in light field camera applications,” in 2016 IEEE 5th Global Conference

on Consumer Electronics. IEEE, 2016, pp. 1–2.

[C42] Y.-A. Hsu, C.-H. Cheng, T.-L. Wu, and Y.-C. Lu, “A prediction method of heat generation in the

silicon substrate for 3-D ICs,” in 2015 IEEE 24th Electrical Performance of Electronic Packaging

and Systems. IEEE, 2015, pp. 89–92.

[C43] Y.-J. Chen, C.-L. Yang, P.-S. Lin, and Y.-C. Lu, “Thermal/performance characterization of CMPs

with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs,” in

2015 Conference on Research in Adaptive and Convergent Systems, 2015, pp. 430–436.

[C44] N.-C. Chen, T.-Y. Chiu, Y.-C. Li, Y.-C. Chien, and Y.-C. Lu, “Power efficient special proces-

sor design for Burrows-Wheeler-Transform-based short read sequence alignment,” in 2015 IEEE

Biomedical Circuits and Systems Conference. IEEE, 2015, pp. 1–4.

[C45] M.-H. Chen, C.-F. Chiang, and Y.-C. Lu, “Depth estimation for hand-held light field cameras

under low light conditions,” in 2014 International Conference on 3D Imaging. IEEE, 2014, pp.

1–4.

[C46] C.-W. Chang, M.-R. Chen, P.-H. Hsu, and Y.-C. Lu, “A pixel-based depth estimation algorithm

and its hardware implementation for 4-D light field data,” in 2014 IEEE International Symposium

on Circuits and Systems. IEEE, 2014, pp. 786–789.

[C47] C.-J. Shih, S.-A. Hsieh, Y.-C. Lu, J. C.-M. Li, T.-L. Wu, and K. Chakrabarty, “Test generation of

path delay faults induced by defects in power TSV,” in 2013 22nd Asian Test Symposium. IEEE,

2013, pp. 43–48.

[C48] C.-L. Kuo, Y.-Y. Lin, and Y.-C. Lu, “Analysis and implementation of Discrete Wavelet Transform

for compressing four-dimensional light field data,” in 2013 IEEE International SOC Conference.

IEEE, 2013, pp. 134–138.

[C49] S.-C. Fan Chiang, P.-H. Hsu, and Y.-C. Lu, “Light field data processor design for depth estimation

using confidence-assisted disparities,” in 2013 IEEE International SOC Conference. IEEE, 2013,

pp. 129–133.

[C50] Y.-L. Huang, C.-S. Liu, Y.-C. Li, and Y.-C. Lu, “Architecture and circuit design of parallel pro-

cessing elements for de novo sequence assembly,” in 2013 IEEE International SOC Conference.

IEEE, 2013, pp. 50–54.

[C51] P.-S. Lin, Y.-J. Chen, C.-L. Yang, and Y.-C. Lu, “Exploring synergistic DVFS control of cores and

DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs,” in International Symposium

on Low Power Electronics and Design. IEEE, 2013, pp. 304–304.

[C52] C.-K. Tang and Y.-C. Lu, “A power-efficient asynchronous circuit style with selective input-channel

restoring,” in 2013 IEEE 56th International Midwest Symposium on Circuits and Systems. IEEE,

2013, pp. 25–28.

[C53] Y.-H. Kuo, C.-S. Liu, Y.-C. Li, and Y.-C. Lu, “Parallel architecture and hardware implementation

of pre-processor and post-processor for sequence assembly,” in 2013 IEEE International Conference

on Acoustics, Speech and Signal Processing. IEEE, 2013, pp. 1158–1161.

[C54] H. Mizunuma, Y.-C. Lu, and C.-L. Yang, “Thermal coupling aware task migration using neigh-

boring core search for many-core systems,” in 2013 International Symposium onVLSI Design,

Automation, and Test. IEEE, 2013, pp. 1–4, Best Paper Award Nominee.

[C55] C.-K. Shen, Y.-C. Lu, Y.-P. Chiou, T.-Y. Cheng, and T.-L. Wu, “Power distribution network

modeling for 3-D ICs with TSV arrays,” in 18th Asia and South Pacific Design Automation

Conference, 2013, pp. 17–22.

[C56] C.-H. Lin, Y.-C. Lu, C.-K. Tang, and K.-Y. Tsai, “The effect of NBTI on 3D integrated circuits,”

in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium. IEEE, 2012,

pp. 201–204.

[C57] Y.-C. Tseng, C.-B. Chang, C.-K. Tang, C.-H. Cheng, Y.-C. Lu, K.-Y. Lin, T.-L. Wu, and R.-

B. Wu, “Design considerations for radio frequency 3DICs,” in 2012 IEEE Electrical Design of

Advanced Packaging and Systems Symposium. IEEE, 2012, pp. 197–200.

[C58] Y.-J. Chang, H.-H. Chuang, Y.-C. Lu, Y.-P. Chiou, T.-L. Wu, P.-S. Chen, S.-H. Wu, T.-Y. Kuo,

C.-J. Zhan, and W.-C. Lo, “Novel crosstalk modeling for multiple through-silicon-vias (TSV) on

3-D IC: Experimental validation and application to Faraday cage design,” in 2012 IEEE 21st

Conference on Electrical Performance of Electronic Packaging and Systems, 2012, pp. 232–235.

[C59] Y.-J. Chang, T.-Y. Zheng, H.-H. Chuang, C.-D. Wang, P.-S. Chen, T.-Y. Kuo, C.-J. Zhan, S.-H.

Wu, W.-C. Lo, Y.-C. Lu, Y.-P. Chiou, and T.-L. Wu, “Low slow-wave effect and crosstalk for

low-cost ABF-coated TSVs in 3-D IC interposer,” in 2012 IEEE 62nd Electronic Components and

Technology Conference. IEEE, 2012, pp. 1934–1938.

[C60] Y.-R. Huang, J.-H. Pan, and Y.-C. Lu, “Thermal-aware router-sharing architecture for 3D

network-on-chip designs,” in 2010 IEEE Asia Pacific Conference on Circuits and Systems. IEEE,

2010, pp. 1087–1090.

[C61] M.-S. Su, K.-Y. Tsai, Y.-C. Lu, Y.-H. Kuo, T.-H. Pei, and J.-Y. Yen, “Architecture for next-

generation massively parallel maskless lithography system (MPML2),” in Alternative Lithographic

Technologies II, vol. 7637. International Society for Optics and Photonics, 2010, p. 76371Q.

[C62] C.-C. Chen, S.-C. F. Chiang, X.-X. Huang, M.-S. Su, and Y.-C. Lu, “Depth estimation of light

field data from pinhole-masked DSLR cameras,” in 2010 IEEE International Conference on Image

Processing. IEEE, 2010, pp. 1769–1772.

[C63] C.-C. Chen, Y.-C. Lu, and M.-S. Su, “Light field based digital refocusing using a DSLR camera

with a pinhole array mask,” in 2010 IEEE International Conference on Acoustics, Speech and

Signal Processing. IEEE, 2010, pp. 754–757.

[C64] K.-Y. Tsai, W.-J. Hsieh, Y.-C. Lu, B.-S. Chang, S.-W. Chien, and Y.-C. Lu, “A new method to

improve accuracy of parasitics extraction considering sub-wavelength lithography effects,” in 2010

15th Asia and South Pacific Design Automation Conference. IEEE, 2010, pp. 651–656.

[C65] H. Mizunuma, C.-L. Yang, and Y.-C. Lu, “Thermal modeling for 3D-ICs with integrated mi-

crochannel cooling,” in 2009 International Conference on Computer-Aided Design, 2009, pp.

256–263, Best Paper Award Nominee.

[C66] Y.-C. Lu, “3D technology based circuit and architecture design,” in 2009 International Conference

on Communications, Circuits and Systems. IEEE, 2009, pp. 1124–1128.

[C67] S.-Y. Cheng, C.-K. Tang, and Y.-C. Lu, “An MSB-first 1-of-N single-track asynchronous add-

compare-select unit for Viterbi decoders,” in 2009 International Conference on Communications,

Circuits and Systems. IEEE, 2009, pp. 361–364.

[C68] Y.-H. Lin, J. Chou, Y.-C. Lu, T.-L. Wu, and H.-S. Chen, “Chip-package-board co-design-a DDR3

system design example from circuit designers’ perspective,” in 2008 Electrical Design of Advanced

Packaging and Systems Symposium. IEEE, 2008, pp. 27–30.

[C69] K.-Y. Tsai, M.-F. You, Y.-C. Lu, and P. C. Ng, “A new method to improve accuracy of leakage

current estimation for transistors with non-rectangular gates due to sub-wavelength lithography

effects,” in 2008 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2008,

pp. 286–291.

[C70] C.-K. Tang, C.-Y. Lin, and Y.-C. Lu, “An asynchronous circuit design with fast forwarding tech-

nique at advanced technology node,” in the 9th International Symposium on Quality Electronic

Design. IEEE, 2008, pp. 769–773.

[C71] T. W. Chen, J. H. Chun, Y.-C. Lu, R. Navid, W. Wang, and R. W. Dutton, “Thermal modeling

and device noise properties of 3D-SOI technology,” in 2007 IEEE International SOI Conference.

IEEE, 2007, pp. 89–90.

[C72] M.-F. You, P. C. Ng, Y.-S. Su, K.-Y. Tsai, and Y.-C. Lu, “Impacts of optical proximity correc-

tion settings on electrical performances,” in Design for Manufacturability through Design-Process

Integration, vol. 6521. International Society for Optics and Photonics, 2007, p. 65210W.

[C73] M. Lin, A. El Gamal, Y.-C. Lu, and S. Wong, “Performance benefits of monolithically stacked

3D-FPGA,” in 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate

Arrays. ACM, 2006, p. 113–122.

[C74] J. W. Kim, Y.-C. Lu, and R. W. Dutton, “Modeling and simulation of jitter in phase-locked

loops due to substrate noise,” in 2005 IEEE International Behavioral Modeling and Simulation

Workshop. IEEE, 2005, pp. 25–30.

[C75] Y.-C. Lu, J. W. Kim, N. Nakano, D. Colleran, P. Yue, and R. W. Dutton, “Realization of digital

noise emulator for characterization of systems exposed to substrate noise,” in the 12th Workshop

on Synthesis and System Integration of Mixed Information Technologies, 2004, pp. 196–203.

[C76] G. Veronis, Y.-C. Lu, and R. W. Dutton, “Modeling of wave behavior of substrate noise coupling

for mixed-signal IC design,” in the 5th International Symposium on Quality Electronic Design.

IEEE, 2004, pp. 303–308.

[C77] H. Lan, Y.-C. Lu, N. Nakano, and R. W. Dutton, “Efficient techniques for reducing complexity of

substrate models in mixed-signal ic’s,” in the 11th Workshop on Synthesis and System Integration

of Mixed Information Technologies, 2003, pp. 83–88.

[C78] Y.-C. Lu, M. Celik, T. Young, and L. T. Pileggi, “Min/max on-chip inductance models and delay

metrics,” in the 38th Annual Design Automation Conference. ACM, 2001, pp. 341–346.

[C79] Y.-C. Lu, K. Banerjee, M. Celik, and R. W. Dutton, “A fast analytical technique for estimating the

bounds of on-chip clock wire inductance,” in 2001 IEEE Custom Integrated Circuits Conference.

IEEE, 2001, pp. 241–244.

ArXiv Paper

[A1] N.-C. Chen, Y.-C. Li, and Y.-C. Lu, “A memory-efficient fm-index constructor for next-generation

sequencing applications on fpgas,” arXiv:2102.03045v1, 2021.

Newsletter and Dissertation

[O1] Y.-J. Chen, C.-L. Yang, P.-S. Lin, and Y.-C. Lu, “Opportunities of synergistically adjusting voltage-

frequency levels of cores and DRAMs in CMPs with 3D-stacked DRAMs for efficient thermal

control,” ACM SIGAPP Applied Computing Review, vol. 16, no. 1, pp. 26–35, 2016.

[O2] Y.-C. Lu, “Digital noise emulator for characterization of phase-locked-loop systems exposed to

substrate noise,” Ph.D. dissertation, Stanford University, 2004.

Patents

[P1] K.-Y. Tsai, M.-F. You, and Y.-C. Lu, “Determining proximity effect parameters for non rectan-

gular semiconductor structures,” Jun. 26 2018, US Patent 10,007,752. (continuation of US Patent

9,087,173).

[P2] ——, “Determining proximity effect parameters for non-rectangular semiconductor structures,”

Jul. 21 2015, US Patent 9,087,173.

[P3] Y.-C. Lu, C.-H. Li, C.-Y. Kuo, and T.-Y. Wu, “Layout of a reference generating system,” Apr. 3

2012, US Patent 8,148,971.

[P4] ——, “Power distribution system,” May 31 2011, US Patent 7,952,229.