Negative Capacitance Field Effect Transistor

Ever-increasing power density in ICs, in which the metal-oxide-semiconductor field effect transistor is the basis of the highly integrated circuits, should be addressed to follow the Moore’s law. The exponential increase of power density arises from the Boltzmann limitation (i.e., the limitation of subthreshold slope of 60 mV/decade) of thermionic emission process operated semiconductor devices such as conventional MOSFETs or FinFETs. To overcome this, negative capacitance (NC) effect was first suggested in 2008 as a solution.

This new component, which is the physical characteristic of ferroelectric layer (PZT, BTO, PVDF, etc.), can give rise to sudden increase in surface potential of conventional FinFET or MOSFET by connecting the ferroelectric capacitor externally of internally in the gate stack. Thereby, SS < 60 mV/decade can be demonstrated. Experimental demonstration for NC effect is actively studied for future semiconductor device.

Quantum Capacitance of Topological Insulator

Topological insulators (TIs) have received great attention because of their unique property, namely, bulk TI material is insulating; however, its surface is in a metallic state. This interesting property is due to the topological surface states (lying in the bulk energy gap) that are protected from scattering events with time-reversal symmetry. At the surface of a TI, there exist topological surface states and a two-dimensional gas (2DEG).

The 2DEG is formed owing to quantum confinement effects on the subsurface of the material. If the 2DEG on the surface of a TI can play the role of the metallic plate in a metal–insulator–semiconductor (MIS) capacitor (e.g., metal–Bi2Te3–SiO2–silicon capacitor), a quantum capacitance (QC) can be obtained owing to the quantum effects of electrons in the 2DEG.

Process-Induced Random Variations

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)

Tunneling FET

As physical sizes of the transistors have been scaled down for decades, inevitable problems such as exponentially increasing power consumption and short channel effects hamper the miniaturization of semiconductor devices. As a breakthrough, a tunnel field effect transistor, which utilizes the band-to-band tunneling nature of carriers instead of thermionic emission process, was investigated as promising next-generation semiconductor device for low power operation.

Recent studies concentrate on enhancing the technical barriers of TFET such as low average subthreshold slope and ambipolar current. Highly enhanced performance of TFET with source region made of novel materials (Ge, SiGe, etc.) with a novel structure (nanowire, etc.) are widely investigated.

Nanoelectromechanical Switch (NEMS)

Following the Moore’s Law, complementary metal oxide semiconductor (CMOS) technology has been scaled down over the past a few decades. As a physical size of metal oxide semiconductor field effect transistor (MOSFET) is shrunk down, its performance, cost per function, and energy efficiency have been improved. However, there exists the fundamental physical limits in scaling down CMOS devices; for example, the subthreshold slope (SS) cannot become lower than 60 mV/decade at 300 K due to non-scalable thermal voltage. Hence, the super steep switching device with sub-60-mV/decade SS is necessary for ultra-low power application.

Based on mechanical switching behavior, the nano-electro-mechanical (NEM) relay has received lots of attention as an alternative of CMOS device because it can not only have a sharp switching feature but also a zero off-state leakage current is achieved.