Journal Publications

1. 1. Shin, C., Cho, M. H., Tsukamoto, Y., Nguyen, B. Y., Mazuré, C., Nikolić, B., & Liu, T. J. K. (2010). Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node. IEEE Transactions on electron devices, 57(6), 1301-1309.

   2. Shin, C., Damrongplasit, N., Sun, X., Tsukamoto, Y., Nikolic, B., & Liu, T. J. K. (2011). Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node. IEEE transactions on electron devices, 58(7), 1846-1854.

   3. Shin, C., Tsai, C. H., Wu, M. H., Chang, C. F., Liu, Y. R., Kao, C. Y., ... & Liu, T. J. K. (2011). Quasi-planar bulk CMOS technology for improved SRAM scalability. Solid-state electronics, 65, 184-190.

   4. Ho, B., Sun, X., Shin, C., & Liu, T. J. K. (2012). Design optimization of multigate bulk MOSFETs. IEEE transactions on electron devices, 60(1), 28-33.

   5. Park, I. J., & Shin, C. (2013). Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs. IEICE Electronics Express, 10(5), 20130108-20130108.

   6. Nam, H., & Shin, C. (2013). Study of high-k/metal-gate work-function variation using Rayleigh distribution. IEEE Electron Device Letters, 34(4), 532-534.

   7. Nam, H., & Shin, C. (2013, April). The design optimization and variation study of segmented-channel MOSFET using HfO 2 or SiO 2 trench isolation. In 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (pp. 1-2). IEEE.

   8. Shin, C., & Park, I. J. (2013). Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage  $ Variation in Quasi-Planar Tri-Gate Bulk MOSFETs. IEEE electron device letters, 34(5), 578-580.

   9. Nam, H., & Shin, C. (2013). Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size. IEICE Electronics Express, 10(9), 20130109-20130109.

   10. Park, I. J., & Shin, C. (2013). Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs. JSTS: Journal of Semiconductor Technology and Science, 13(5), 511-515.

   11. Damrongplasit, N., Kim, S. H., Shin, C., & Liu, T. J. K. (2013). Impact of gate line-edge roughness (LER) versus random dopant fluctuations (RDF) on germanium-source tunnel FET performance. IEEE transactions on nanotechnology, 12(6), 1061-1067.

   12. Nam, H., & Shin, C. (2013). Study of High-$ k $/Metal-Gate Work Function Variation in FinFET: The Modified RGG Concept. IEEE electron device letters, 34(12), 1560-1562.

   13. Nam, H., Lee, G. S., Lee, H., Park, I. J., & Shin, C. (2014). Analysis of random variations and variation-robust advanced device structures. JSTS: Journal of Semiconductor Technology and Science, 14(1), 8-22.

   14. Lee, G. S., & Shin, C. (2014). Computing-Inexpensive Matrix Model for Estimating the Threshold Voltage Variation by Workfunction Variation in High-κ/Metal-gate MOSFETs. JSTS: Journal of Semiconductor Technology and Science, 14(1), 96-99.

   15. Shin, C. (2014). State-of-the-art silicon device miniaturization technology and its challenges. IEICE Electronics Express, 11(10), 20142005-20142005.

   16. Shin, C. (2014). Assistive circuit for lowering minimum operating voltage and balancing read/write margins in an SRAM array. JSTS: Journal of Semiconductor Technology and Science, 14(2), 184-188.

   17. Nam, H., & Shin, C. (2014). Impact of current flow shape in tapered (versus rectangular) FinFET on threshold voltage variation induced by work-function variation. IEEE Transactions on Electron Devices, 61(6), 2007-2011.

   18. Kim, J. K., Kim, G. S., Shin, C., Park, J. H., Saraswat, K. C., & Yu, H. Y. (2014). Analytical study of interfacial layer doping effect on contact resistivity in metal-interfacial layer-Ge structure. IEEE electron device letters, 35(7), 705-707.

   19. Moon, D., Lee, H., Shin, C., & Shin, H. (2014). Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application. IEICE Electronics Express, 11(13), 20140468-20140468.

   20. Shin, C., Lee, G. G., Han, D. H., Han, S. P., Tokumitsu, E., Ohmi, S. I., ... & Park, B. E. (2014). Experimental demonstration of a ferroelectric FET using paper substrate. IEICE Electronics Express, 11-20140447.

   21. Nam, H., Park, S., & Shin, C. (2014). Performance and variation-immunity benefits of segmented-channel MOSFETs (SegFETs) using HfO 2 or SiO 2 trench isolation. JSTS: Journal of Semiconductor Technology and Science, 14(4), 427-435.

   22. Kim, G. S., Kim, J. K., Kim, S. H., Jo, J., Shin, C., Park, J. H., ... & Yu, H. Y. (2014). Specific contact resistivity reduction through Ar plasma-treated TiO 2− x interfacial layer to metal/Ge contact. IEEE Electron Device Letters, 35(11), 1076-1078.

   23. Park, I. J., Jeon, S. G., & Shin, C. (2014). A new slit-type vacuum-channel transistor. IEEE Transactions on electron devices, 61(12), 4186-4191.

   24. Kim, J. K., Kim, G. S., Nam, H., Shin, C., Park, J. H., Kim, J. K., ... & Yu, H. Y. (2014). The efficacy of metal-interfacial layer-semiconductor source/drain structure on sub-10-nm n-type Ge FinFET performances. IEEE Electron Device Letters, 35(12), 1185-1187.

   25. Jo, J., & Shin, C. (2015). Impact of temperature on negative capacitance field-effect transistor. Electronics Letters, 51(1), 106-108.

   26. Nam, H., Cho, M. H., & Shin, C. (2015). Symmetric tunnel field-effect transistor (S-TFET). Current Applied Physics, 15(2), 71-77.

   27. Jo, J., & Shin, C. (2015). Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices. Current Applied Physics, 15(3), 352-355.

   28. Jung, H., Chae, S. Y., Shin, C., Min, B. K., Joo, O. S., & Hwang, Y. J. (2015). Effect of the Si/TiO2/BiVO4 heterojunction on the onset potential of photocurrents for solar water oxidation. ACS Applied Materials & Interfaces, 7(10), 5788-5796.

   29. Kwon, W., Park, I. J., & Shin, C. (2015). Highly scalable NAND flash memory cell design embracing backside charge storage. JSTS: Journal of Semiconductor Technology and Science, 15(2), 286-291.

   30. Oh, S., Jo, J., Lee, H., Lee, G. S., Park, J. D., & Shin, C. (2015). Worst case sampling method with confidence ellipse for estimating the impact of random variation on static random access memory (SRAM). JSTS: Journal of Semiconductor Technology and Science, 15(3), 374-380.

   31. Lee, H., Park, S., Lee, Y., Nam, H., & Shin, C. (2014). Random variation analysis and variation-aware design of symmetric tunnel field-effect transistor. IEEE Transactions on Electron Devices, 62(6), 1778-1783.

   32. Lee, G. S., & Shin, C. (2014). Worst case sampling method to estimate the impact of random variation on static random access memory. IEEE Transactions on Electron Devices, 62(6), 1705-1709.

   33. Park, S., Lee, J. H., & Shin, C. (2015). Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor. IEICE Electronics Express, 12(12), 20150349-20150349.

   34. Lee, Y., Nam, H., Park, J. D., & Shin, C. (2015). Study of work-function variation for high-$\kappa $/metal-gate Ge-Source tunnel field-effect transistors. IEEE Transactions on Electron Devices, 62(7), 2143-2147.

   35. Jo, J., Choi, W. Y., Park, J. D., Shim, J. W., Yu, H. Y., & Shin, C. (2015). Negative capacitance in organic/ferroelectric capacitor to implement steep switching MOS devices. Nano letters, 15(7), 4553-4556.

   36. Kim, G. S., Kim, S. H., Kim, J. K., Shin, C., Park, J. H., Saraswat, K. C., ... & Yu, H. Y. (2015). Surface passivation of germanium using SF 6 plasma to reduce source/drain contact resistance in germanium n-FET. IEEE Electron Device Letters, 36(8), 745-747.

   37. Kim, S. H., Kim, G. S., Kim, J. K., Park, J. H., Shin, C., Choi, C., & Yu, H. Y. (2015). Fermi-level unpinning using a Ge-passivated metal–interlayer–semiconductor structure for non-alloyed ohmic contact of high-electron-mobility transistors. IEEE Electron Device Letters, 36(9), 884-886.

   38. Oh, S., Shin, C., & Kwon, W. (2015). A compact effective-current model for power performance analysis on state-of-the-art technology development and benchmarking. Japanese Journal of Applied Physics, 54(12), 124302.

   39. Jo, J., & Shin, C. (2016). Negative capacitance field effect transistor with hysteresis-free sub-60-mV/decade switching. IEEE Electron Device Letters, 37(3), 245-248.

   40. Lee, H., Cho, K., Shin, C., & Shin, H. (2016). Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor. JSTS: Journal of Semiconductor Technology and Science, 16(2), 185-190.

   41. Lee, H., Park, J. D., & Shin, C. (2016). Study of random variation in germanium-source vertical tunnel FET. IEEE Transactions on Electron Devices, 63(5), 1827-1834.

   42. Oh, S., & Shin, C. (2016). Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method. IEICE Transactions on Electronics, 99(5), 541-543.

   43. Cho, K., Jo, J., & Shin, C. (2016). Amorphous Indium Zinc Oxide Thin-Film Transistor with Steep Subthreshold Slope by Negative Capacitance. IEICE Transactions on Electronics, 99(5), 544-546.

   44. Shin, C., Kim, J. K., Shin, C., Kim, J. K., & Yu, H. Y. (2016). Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure. Current Applied Physics, 16(6), 618-622.

   45. Cho, K., Park, J. D., & Shin, C. (2016). Atomic layer deposition of TiO 2 using titanium isopropoxide and H 2 O: operational principle of equipment and parameter setting. JSTS: Journal of Semiconductor Technology and Science, 16(3), 346-351.

   46. Ahn, J., Kim, J. K., Kim, S. W., Kim, G. S., Shin, C., Kim, J. K., ... & Yu, H. Y. (2016). Effect of metal nitride on contact resistivity of metal-interlayer-Ge source/drain in sub-10-nm n-type Ge FinFET. IEEE Electron Device Letters, 37(6), 705-708.

   47. Kim, G. S., Yoo, G., Seo, Y., Kim, S. H., Cho, K., Cho, B. J., ... & Yu, H. Y. (2016). Effect of hydrogen annealing on contact resistance reduction of metal–interlayer–n-germanium source/drain structure. IEEE Electron Device Letters, 37(6), 709-712.

   48. Nam, H., Lee, Y., Park, J. D., & Shin, C. (2016). Study of Work-Function Variation in High-$\kappa $/Metal-Gate Gate-All-Around Nanowire MOSFET. IEEE Transactions on Electron Devices, 63(8), 3338-3341.

   49. Shin, C., Kim, J. K., Kim, G. S., Lee, H., Shin, C., Kim, J. K., ... & Yu, H. Y. (2016). Random dopant fluctuation-induced threshold voltage variation-immune Ge FinFET with metal–interlayer–semiconductor source/drain. ieee transactions on electron devices, 63(11), 4167-4172.

   50. Lee, H., Park, J. D., & Shin, C. (2016). Performance Booster for Vertical Tunnel Field-Effect Transistor: Field-Enhanced High-$\kappa $ Layer. IEEE Electron Device Letters, 37(11), 1383-1386.

   51. Oh, S., & Shin, C. (2016). 3-D quasi-atomistic model for line edge roughness in nonplanar MOSFETs. IEEE Transactions on Electron Devices, 63(12), 4617-4623.

   52. Park, J., Lee, H., Oh, S., & Shin, C. (2016). Design for variation-immunity in sub-10-nm stacked-nanowire FETs to suppress LER-induced random variations. IEEE Transactions on Electron Devices, 63(12), 5048-5054.

   53. Ko, E., Lee, H., Park, J. D., & Shin, C. (2016). Vertical tunnel FET: Design optimization with triple metal-gate layers. IEEE Transactions on Electron Devices, 63(12), 5030-5035.

   54. Choi, H., Lee, H., Park, J., Yu, H. Y., Kim, T. G., & Shin, C. (2016). Experimental evidence of negative quantum capacitance in topological insulator for sub-60-mV/decade steep switching device. Applied Physics Letters, 109(20), 203505.

   55. Kim, G. S., Kim, S. W., Kim, S. H., Park, J., Seo, Y., Cho, B. J., Shin, C.,  ... & Yu, H. Y. (2016). Effective Schottky barrier height lowering of metal/n-Ge with a TiO2/GeO2 interlayer stack. ACS Applied Materials & Interfaces, 8(51), 35419-35425.

   56. Ko, E., Lee, J. W., & Shin, C. (2017). Negative capacitance FinFET with sub-20-mV/decade subthreshold slope and minimal hysteresis of 0.48 V. IEEE Electron Device Letters, 38(4), 418-421.

   57. Choi, H., Shin, J., & Shin, C. (2017). Impact of source/drain metal work function on the electrical characteristics of anatase TiO2-based thin film transistors. ECS Journal of Solid State Science and Technology, 6(7), P379.

   58. Lee, Y., Jo, J., Cho, K., Oh, S., Park, J. D., & Shin, C. (2017). Experimental Observation of Negative Capacitance in Organic/Ferroelectric Capacitor for Steep Switching MOSFET. Journal of Nanoscience and Nanotechnology, 17(5), 3469-3471.

   59. Ku, H., & Shin, C. (2017). Transient response of negative capacitance in P (VDF 0.75-TrFE 0.25) organic ferroelectric capacitor. IEEE Journal of the Electron Devices Society, 5(3), 232-236.

   60. Lee, Y., & Shin, C. (2017). Impact of equivalent oxide thickness on threshold voltage variation induced by work-function variation in multigate devices. IEEE Transactions on Electron Devices, 64(5), 2452-2456.

   61. Lee, H., Yoon, Y., & Shin, C. (2017). Current-voltage model for negative capacitance field-effect transistors. IEEE Electron Device Letters, 38(5), 669-672.

   62. Yeom, S. W., You, B., Cho, K., Jung, H. Y., Park, J., Shin, C., ... & Kim, J. W. (2017). Silver nanowire/colorless-polyimide composite electrode: application in flexible and transparent resistive switching memory. Scientific reports, 7(1), 1-9.

   63. Choi, H., Kim, T. G., & Shin, C. (2017). Measurement of the quantum capacitance from two-dimensional surface state of a topological insulator at room temperature. Applied Surface Science, 407, 16-20.

   64. Ko, E., Lee, H., Goh, Y., Jeon, S., & Shin, C. (2017). Sub-60-mV/decade negative capacitance FinFET with sub-10-nm hafnium-based ferroelectric capacitor. IEEE Journal of the Electron Devices Society, 5(5), 306-309.

   65. Park, J., & Shin, C. (2017). Impact of interface traps and surface roughness on the device performance of stacked-nanowire FETs. IEEE Transactions on Electron Devices, 64(10), 4025-4030.

   66. Kim, G. S., Kim, S. H., Lee, T. I., Cho, B. J., Choi, C., Shin, C., ... & Yu, H. Y. (2017). Fermi-level unpinning technique with excellent thermal stability for n-type germanium. ACS applied materials & interfaces, 9(41), 35988-35997.

   67. Ko, E., & Shin, C. (2017). Effective drive current in steep slope FinFET (vs. conventional FinFET). Applied Physics Letters, 111(15), 152105.

   68. Choe, K., & Shin, C. (2017). Adjusting the operating voltage of an nanoelectromechanical relay using negative capacitance. IEEE Transactions on Electron Devices, 64(12), 5270-5273.

   69. Jo, J., Kim, M. G., Lee, H., Choi, H., & Shin, C. (2017). Transconductance amplification by the negative capacitance in ferroelectric-gated P3HT thin-film transistor. IEEE Transactions on Electron Devices, 64(12), 4974-4979.

   70. Shin, J., Ko, E., & Shin, C. (2017). Analysis on the operation of negative differential resistance FinFET with Pb (Zr 0.52 Ti 0.48) O 3 threshold selector. IEEE Transactions on Electron Devices, 65(1), 19-22.

   71. Ku, H., & Shin, C. (2018). Comparative Study of Negative Capacitance in Ferroelectric Capacitors: P (VDF 0.75-TrFE 0.25) Versus Pb (Zr, Ti) O₃. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 18(2), 167-171.

   72. Ku, H., & Shin, C. (2018). Comparative Study of Negative Differential Capacitance in Ferroelectric Capacitors: P (VDF 0.75-TrFE 0.25) and P (VDF 0.50-TrFE 0.50). JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 18(3), 321-327.

   73. Choe, K., & Shin, C. (2018). Tapered Coating for Nano-electro-mechanical (NEM) Relay to Improve Energy-delay Product. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 18(3), 367-372.

   74. Cho, K., & Shin, C. (2018). Simulation Techniques for Nanoelectromechanical (NEM) Relay. Journal of Nanoscience and Nanotechnology, 18(9), 6615-6618.

   75. Shin, J., Ko, E., Park, J., Kim, S. G., Lee, J. W., Yu, H. Y., & Shin, C. (2018). Super steep-switching (SS≈ 2 mV/decade) phase-FinFET with Pb (Zr0. 52Ti0. 48) O3 threshold switching device. Applied Physics Letters, 113(10), 102104.

   76. Nam, H., Shin, C., & Park, J. D. (2018). Impact of the Metal-Gate Material Properties in FinFET (Versus FD-SOI MOSFET) on High-$\kappa $/Metal-Gate Work-Function Variation. IEEE Transactions on Electron Devices, 65(11), 4780-4785.

   77. Ko, E., Shin, J., & Shin, C. (2018). Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors. Nano Convergence, 5(1), 1-9.

   78. Shin, J., & Shin, C. (2018). External resistor-free gate configuration phase transition FDSOI MOSFET. IEEE Journal of the Electron Devices Society, 7, 186-190.

   79. Choi, H., Park, J., Shim, J. W., & Shin, C. (2019). Negative quantum capacitance effect from Bi2Te1. 5Se1. 5 with frequency dependent capacitance of polyvinyl alcohol (PVA) film in MOS structure. Applied Surface Science, 463, 1046-1050.

   80. Lee, C., Ko, E., & Shin, C. (2018). Steep slope silicon-on-insulator feedback field-effect transistor: Design and performance analysis. IEEE Transactions on Electron Devices, 66(1), 286-291.

   81. Choe, K., & Shin, C. (2018). Ferroelectric-gated nanoelectromechanical nonvolatile memory cell. IEEE Transactions on Electron Devices, 66(1), 407-412.

   82. Cho, H., & Shin, C. (2019). DIBL enhancement in ferroelectric-gated FinFET. Semiconductor Science and Technology, 34(2), 025004.

   83. Shin, S. C., Koh, C. W., Vincent, P., Goo, J. S., Bae, J. H., Lee, J. J., ... & Shim, J. W. (2019). Ultra-thick semi-crystalline photoactive donor polymer for efficient indoor organic photovoltaics. Nano Energy, 58, 466-475.

   84. Shin, J., & Shin, C. (2019). Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET. Solid-State Electronics, 153, 12-15.

   85. Choe, K., & Shin, C. (2019). Impact of negative capacitance on the energy-delay property of an electromechanical relay. Japanese Journal of Applied Physics, 58(5), 051003.

   86. You, Y. J., Kim, Y., Cheun, H., Shin, C., Lee, J. H., Song, J. Y., ... & Shim, J. W. (2019). Precise control of nanoscale spacing between electrodes using different natured self-assembled monolayers. Nanotechnology, 30(26), 265302.

   87. Cho, H., Shin, J., & Shin, C. (2019). Impact of Ferroelectric Capacitor’s Electrode Area on the Performance of Negative Capacitance Field Effect Transistor. Journal of Nanoscience and Nanotechnology, 19(10), 6087-6090.

   88. Park, J., & Shin, C. (2019). Process-induced random variation: Work-function variation in stacked nanowire field effect transistor. Journal of nanoscience and nanotechnology, 19(10), 6091-6094.

   89. Ko, E., Shin, J., & Shin, C. (2019). Steep Slope Silicon-on-Insulator Field Effect Transistor with Negative Capacitance: Analysis on Hysteresis. Journal of Nanoscience and Nanotechnology, 19(10), 6128-6130.

   90. Shin, J., & Shin, C. (2019). DIBL improvement in hysteresis-free and ferroelectric-gated FinFETs. Semiconductor Science and Technology, 34(6), 065001.

   91. Park, J., & Shin, C. (2019). Tunnel field-effect transistor with segmented channel. IEEE Journal of the Electron Devices Society, 7, 621-625.

   92. Shin, C. (2019). Experimental understanding of polarization switching in PZT ferroelectric capacitor. Semiconductor Science and Technology, 34(7), 075004.

   93. Choi, H., & Shin, C. (2019). Negative capacitance transistor with two‐dimensional channel material (Molybdenum disulfide, MoS2). physica status solidi (a), 216(16), 1900177.

   94. Shim, J., woon Jang, S., Lim, J. H., Kim, H., Kang, D. H., Kim, K. H., Shin, C. H., ... & Park, J. H. (2019). Polarity control in a single transition metal dichalcogenide (TMD) transistor for homogeneous complementary logic circuits. Nanoscale, 11(27), 12871-12877.

   95. Yoon, J. S., Tewari, A., Shin, C., & Jeon, S. (2019). Influence of high-pressure annealing on memory properties of Hf 0.5 Zr 0.5 O 2 based 1T-FeRAM. IEEE Electron Device Letters, 40(7), 1076-1079.

   96. Choe, K., Park, J., & Shin, C. (2020). Theoretical study of ferroelectric-gated nanoelectromechanical diode nonvolatile memory cell. Solid-State Electronics, 163, 107662.

   97. Park, J., & Shin, C. (2019). Study of work-function variation in stacked multiple-channel-structure device. Semiconductor Science and Technology, 34(12), 125003.

   98. Min, J., & Shin, C. (2019). Study of line edge roughness on various types of gate-all-around field effect transistor. Semiconductor Science and Technology, 35(1), 015004.

   99. Choi, Y., Hong, Y., & Shin, C. (2019). Device design guideline for junctionless gate-all-around nanowire negative-capacitance FET with HfO2-based ferroelectric gate stack. Semiconductor Science and Technology, 35(1), 015011.

   100. Yoon, C., & Shin, C. (2020). Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices. Solid-State Electronics, 164, 107698.

   101. Park, J., & Shin, C. (2020). Study of random dopant fluctuation in PNPN feedback FET. Semiconductor Science and Technology, 35(3), 035019.

   102. Hong, Y., Choi, Y., & Shin, C. (2020). NCFET-based 6-T SRAM: Yield estimation based on variation-aware sensitivity. IEEE Journal of the Electron Devices Society, 8, 182-188.

   103. Lee, C., & Shin, C. (2020). Study on various device structures for steep-switching silicon-on-insulator feedback field-effect transistors. IEEE Transactions on Electron Devices, 67(4), 1852-1858.

   104. Yoon, C., Choe, G., & Shin, C. (2020). Energy-delay sensitivity analysis of a nanoelectromechanical relay with the negative capacitance of a ferroelectric capacitor. IEEE Journal of the Electron Devices Society, 8, 365-372.

   105. Wang, C. W., Ku, H., Chiu, C. Y., De, S., Qiu, B. H., Shin, C., & Lu, D. (2020). Compact model for PZT ferroelectric capacitors with voltage dependent switching behavior. Semiconductor Science and Technology, 35(5), 055033.

   106. Lee, C., Sung, J., & Shin, C. (2020). Understanding of feedback field-effect transistor and its applications. Applied Sciences, 10(9), 3070.

   107. Moon, S., Shin, J., & Shin, C. (2020). Understanding of polarization-induced threshold voltage shift in ferroelectric-gated field effect transistor for neuromorphic applications. Electronics, 9(5), 704.

   108. Choi, Y., Hong, Y., Ko, E., & Shin, C. (2020). Optimization of double metal-gate InAs/Si heterojunction nanowire TFET. Semiconductor Science and Technology, 35(7), 075024.

   109. Jung, T., & Shin, C. (2020). Device-design optimization of ferroelectric-gated vertical tunnel field-effect transistor to suppress ambipolar current. Semiconductor Science and Technology, 35(8), 085010.

   110. Choi, Y., Shin, J., Moon, S., & Shin, C. (2020). Investigation on Threshold Voltage Adjustment of Threshold Switching Devices with HfO2/Al2O3 Superlattice on Transparent ITO/Glass Substrate. Micromachines, 11(5), 525.

   111. Seo, J., & Shin, C. (2020). Experimental study of interface traps in MOS capacitor with Al-doped HfO2. Semiconductor Science and Technology, 35(8), 085029.

   112. Yoon, C., Min, J., Shin, J., & Shin, C. (2020). Device Design Guideline for HfO₂-Based Ferroelectric-Gated Nanoelectromechanical System. IEEE Journal of the Electron Devices Society, 8, 608-613.

   113. Yoon, C., & Shin, C. (2020). Electrical Characteristics of Nanoelectromechanical Relay with Multi-Domain HfO2-Based Ferroelectric Materials. Electronics, 9(8), 1208.

   114. Yoon, C., Moon, S., & Shin, C. (2020). Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor. Nano Convergence, 7(1), 1-7.

   115. Min, J., & Shin, C. (2020). MFMIS negative capacitance FinFET design for improving drive current. Electronics, 9(9), 1423.

   116. Min, J., Choe, G., & Shin, C. (2020). Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs. Current Applied Physics, 20(11), 1222-1225.

   117. Lim, J., & Shin, C. (2020). Machine learning (ML)-based model to characterize the line edge roughness (LER)-induced random variation in FinFET. IEEE Access, 8, 158237-158242.

   118. Park, J., Kim, J., Showdhury, S., Shin, C., Rhee, H., Yeo, M. S., ... & Yi, J. (2020). Electrical characteristics of bulk FinFET according to spacer length. Electronics, 9(8), 1283.

   119. Jung, T., Shin, J., & Shin, C. (2020). Impact of depolarization electric-field and charge trapping on the coercive voltage of an Si: HfO2-based ferroelectric capacitor. Semiconductor Science and Technology, 36(1), 015005.

   120. Das, D., Kim, T., Gaddam, V., Shin, C., & Jeon, S. (2020). Trade-off between interfacial charge and negative capacitance effects in the Hf-Zr-Al-O/Hf0. 5Zr0. 5O2 bilayer system. Solid-State Electronics, 174, 107914.

   121. Kim, T., & Shin, C. (2020). Effects of Interface Trap on Transient Negative Capacitance Effect: Phase Field Model. Electronics, 9(12), 2141.

   122. Sung, J., & Shin, C. (2020). Recent studies on supercapacitors with next-generation structures. Micromachines, 11(12), 1125.

   123. Yu, S., & Shin, C. (2021). Quantitative evaluation of process-induced line-edge roughness in FinFET: Bayesian regression model. Semiconductor Science and Technology, 36(2), 025020.

   124. Lee, J., Park, T., Ahn, H., Kwak, J., Moon, T., & Shin, C. (2021). Prediction model for random variation in FinFET induced by line-edge-roughness (LER). Electronics, 10(4), 455.

   125. Jung, S. G., Park, E., Shin, C., & Yu, H. Y. (2021). LER-induced random variation–immune effect of metal-interlayer–semiconductor source/drain structure on N-type Ge Junctionless FinFETs. IEEE Transactions on Electron Devices, 68(3), 1340-1345.

   126. Han, S., Jeong, S., Shin, J., & Shin, C. (2021). Steep-Switching Fully Depleted Silicon-on-Insulator (FDSOI) Phase-Transition Field-Effect Transistor With Optimized HfO₂/Al₂O₃-Multilayer-Based Threshold Switching Device. IEEE Transactions on Electron Devices, 68(3), 1358-1363.

   127. Lee, C., & Shin, C. (2021). FBFET (feedback field-effect transistor)-based oscillator for neuromorphic computing. Semiconductor Science and Technology, 36(3), 035013.

   128. Han, S., Jeong, S., Shin, J., & Shin, C. (2021). Steep-Switching Fully Depleted Silicon-on-Insulator (FDSOI) Phase-Transition Field-Effect Transistor With Optimized HfO₂/Al₂O₃-Multilayer-Based Threshold Switching Device. IEEE Transactions on Electron Devices, 68(3), 1358-1363.

   129. Yu, H., & Shin, C. (2021). Impact of Rapid-Thermal-Annealing Temperature on the Polarization Characteristics of a PZT-Based Ferroelectric Capacitor. Electronics, 10(11), 1324.

   130. Jung, T., O’Sullivan, B. J., Ronchi, N., Linten, D., Shin, C., & Van Houdt, J. (2021). Impact of Interface Layer on Device Characteristics of Si: HfO 2-Based FeFET’s. IEEE Transactions on Device and Materials Reliability, 21(2), 176-182.

   131. Jung, T., & Shin, C. (2021). Experimental study of threshold voltage shift for Si: HfO2 based ferroelectric field effect transistor. Nanotechnology, 32(37), 375203.

   132. Lim, J., Lee, J., & Shin, C. (2021). Probabilistic artificial neural network for line-edge-roughness-induced random variation in FinFET. IEEE Access, 9, 86581-86589.

   133. Hong, Y., Choi, Y., & Shin, C. (2020). NCFET-based 6-T SRAM: Yield estimation based on variation-aware sensitivity. IEEE Journal of the Electron Devices Society, 8, 182-188.

   134. Park, J., Jang, W., & Shin, C. (2021). Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device. Micromachines, 12(8), 886.

   135. Min, J., Ronchi, N., McMitchell, S. R., O’Sullivan, B., Banerjee, K., Van Houdt, J., & Shin, C. (2021). Program/Erase Scheme for Suppressing Interface Trap Generation in HfO 2-Based Ferroelectric Field Effect Transistor. IEEE Electron Device Letters, 42(9), 1280-1283.

   136. Choi, Y., Lee, J., Lim, J., Moon, S., & Shin, C. (2021). Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET. Electronics, 10(16), 1899.

   137. Jeong, S., Han, S., Lee, H. J., Eom, D., Youm, G., Choi, Y., ... & Shin, C. (2021). Abruptly-Switching MoS₂-Channel Atomic-Threshold-Switching Field-Effect Transistor With AgTi/HfO₂-Based Threshold Switching Device. IEEE Access, 9, 116953-116961.

   138. Jung, D., Kang, K., Jung, H., Seong, D., An, S., Yoon, J., ... & Son, D. (2021). A soft pressure sensor array based on a conducting nanomembrane. Micromachines, 12(8), 933.

   139. Lee, S., Choi, Y., Won, S. M., Son, D., Baac, H. W., & Shin, C. (2022). Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications. Semiconductor Science and Technology, 37(3), 035019.

   140. Lee, C., Han, C., & Shin, C. (2022). Inverter design with positive feedback field-effect transistors. Semiconductor Science and Technology, 37(3), 035014. 

   141. Yu, S., Won, S. M., Baac, H. W., Son, D., & Shin, C. (2022). Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection. IEEE Access, 10, 26340-26346. 

   142. Lee, S., Choi, Y., Won, S. M., Son, D., Baac, H. W., & Shin, C. (2022). Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications. Semiconductor Science and Technology, 37(3), 035019. 

   143. Faraz, M., Abbasi, M. A., Son, D., Shin, C., Lee, K. T., Won, S. M., & Baac, H. W. (2022). Strain-Dependent Photoacoustic Characteristics of Free-Standing Carbon-Nanocomposite Transmitters. Sensors, 22(9), 3432. 

   144. Choi, Y., Han, C., Shin, J., Moon, S., Min, J., Park, H., ... & Shin, C. (2022). Impact of Chamber/Annealing Temperature on the Endurance Characteristic of Zr: HfO2 Ferroelectric Capacitor. Sensors, 22(11), 4087. 

   145. Han, S., Kim, Y., Son, D., Baac, H. W., Won, S. M., & Shin, C. (2022). Study on memory characteristics of fin-shaped feedback field effect transistor. Semiconductor Science and Technology, 37(6), 065006. 

   146. Baek, S., Yoo, H. H., Ju, J. H., Sriboriboon, P., Singh, P., Niu, J., ... & Lee, S. (2022). Ferroelectric Field‐Effect‐Transistor Integrated with Ferroelectrics Heterostructure. Advanced Science, 9(21), 2200566. 

   147. Lee, D., & Shin, C. (2022). Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages. Micromachines, 13(7), 1139. 

   148. Lim, D., Hong, I., Park, S. U., Chae, J. W., Lee, S., Baac, H. W., ... & Won, S. M. (2022). Functional Encapsulating Structure for Wireless and Immediate Monitoring of the Fluid Penetration. Advanced Functional Materials, 32(31), 2201854. 

   149. Sun, M., Baac, H. W., & Shin, C. (2022). Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM. Micromachines, 13(9), 1476. 

   150. Noh, C., Han, C., Won, S. M., & Shin, C. (2022). Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology. Micromachines, 13(9), 1551. 

   151. Choi, Y., Park, H., Han, C., Min, J., & Shin, C. (2022). Improved remnant polarization of Zr-doped HfO2 ferroelectric film by CF4/O2 plasma passivation. Scientific Reports, 12(1), 16750. 

   152. Sung, J., & Shin, C. (2022). Understanding of carriers’ kinetic energy in steep-slope P+ N+ P+ N+ feedback field effect transistor. Semiconductor Science and Technology, 37(10), 105014. 

   153. Kim, G., Lim, J., Eom, D., Choi, Y., Kim, H., & Shin, C. (2022). Impact of Various Pulse-Bases on Charge Boost in Ferroelectric Capacitors. IEEE Electron Device Letters, 43(11), 1953-1956. 

   154. Park, T., Kwak, J., Ahn, H., Lee, J., Lim, J., Yu, S., ... & Moon, T. (2022). GAN-Based Framework for Unified Estimation of Process-Induced Random Variation in FinFET. IEEE Access, 10, 130001-130023. 

   155. Choi, Y., Shin, J., Moon, S., Min, J., Han, C., & Shin, C. (2023). Experimental study of endurance characteristics of Al-doped HfO2 ferroelectric capacitor. Nanotechnology. 

   156. Lee, S., Ronchi, N., Bizindavyi, J., Popovici, M. I., Banerjee, K., Walke, A., ... & Shin, C. (2023). Analysis of Wake-Up Reversal Behavior Induced by Imprint in La:HZO MFM Capacitors. IEEE Transactions on Electron Devices, 70(5), 2568-2574.

   157. Choi, Y., Park, H., Han, C., & Shin, C. (2023). Impact of CF4/O2 Plasma Passivation on Endurance Performance of Zr-Doped HfO2 Ferroelectric Film. IEEE Electron Device Letters, 44(5), 713-716.

   158. Son, M., Sung, J., Baac, H. W., & Shin, C. (2023). Comparative study of novel u-shaped SOI FinFET against multiple-fin bulk/SOI FinFET. IEEE Access, 11, 96170-96176.

   159. Lim, J., Han. D., Baac, H. W., & Shin, C. (2023). Design for Variability: Counter-Doped Source/Drain Epitaxy Pockets in Gate-All-Around FET. IEEE Transactions on Electron Devices, 71(1), 400-405.

   160. Yoon, J., Choi, Y., & Shin, C. (2024). Grain-size adjustment in Hf0.5Zr0.5O2 ferroelectric film to improve the switching time in  Hf0.5Zr0.5O2  -based ferroelectric capacitor. Nanotechnology 35(13), 135203.

   161. Im, S., Jeong, J. S., Shin, C., Cho, J. H., & Ju, H. (2024). Column Row Convolutional Neural Network: Reducing Parameters for Efficient Image Processing. Neural Computation, 36(4), 744-758.

   162. Park, I., Choi, Y., & Chin, C. (2024). Impact of the Crystal Structure of Interlayer on the Properties of Zr‐Doped Hafnia‐Based Ferroelectric Capacitor. physica status solidi (a), 221(9),2300778.

   163. Chu, D., Kang, S., Kim, G., Sung, J., Lim, J., Choi, Y., Han, D., & Chin, C. (2024). First integration of Ni barrier layer for enhanced threshold switching characteristics in Ag/HfO2-based TS device. Materials Today Advances, 22, 100492.

   164. Chu, D., Han, D., Kang. S., Kim, G., Choi, Y., Jang, E., & Shin, C. (2024). Self-Healing Magnetic Field-Assisted Threshold switching Device Utilizing Dual Field-Driven Filamentary Physics. Advanced Electronics Materials, 2400140.

   165. Sung, J., Kang. S., Han, D., Kim, G., Son, M., & Shin, C. (2024). Sub-Boltzmann Switching, Hysteresis-Free Charge Modulated Negative Differential Resistance  FinFET. ACS Nano.

   166. Yoon, J., Yoon, S., Ahn, J., & Shin, C. (2024). Row Hammer-Induced D0 Failure Improvement in  Sub-20 nm DRAM Using Air Gap. Semiconductor Science and Technology, 39(12), 125016.

   167. Choi, Y., Shin, J., Min, J., Moon, S., Chu, D., Han, D., & Shin, C. (2024). Oxygen Reservoir Effect of Tungsten Trioxide Electrode on Endurance Performance of Metal-Ferroelectric-Metal Capacitors for FeRAM Applications. Scientific Report, 14(1), 28912.

   168. Jang, E., Kim, M., & Shin, C. (2024). Taper-angle-induced variation in n/p-stacked vs. p/n-stacked CFET. IEEE Transactions on Electron Devices, 72(1), 90-96.

   169. Yoon, S., Yoon, J., & Shin, C. (2024). Variation-aware analysis of buried-channel-array transistors (BCATs) in scaled DRAM: insights from 3D quasi-atomistic simulations. Semiconductor Science and Technology, 40(1), 015010.

   170. Jang, E., Lim, J., & Shin, C. (2024). Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET). Nano Express, 5(4), 045021.

   171. Lim, J., Han, D., Sung, J., Yoon, S., Kang, S., Kim, G., Bacc, H.,  & Shin, C. (2025). Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(8), 3189-3196.

   172. Lim, J., Yoon, S., Sung, J., Kang, S., Kim, G., Bacc, H.,  & Shin, C. (2025). Study of 3D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(9), 3571-3580.

   173. Kim, G., Sung, J., Kang, S., Lim, J., & Shin, C. (2025). Investigation of the Switching Mechanism in the Bipolar and Complementary Resistive Switching of HfOx-Based Resistive Random-Access Memory through Rapid-Thermal-Annealing-Induced Grain Boundary Engineering. ACS Applied Electronic Materials, 7(8), 3561-3570.

   174. Lee, T., & Shin, C. (2025). Comparative analysis of NMOS-/PMOS-based 3D Fe-NAND using TCAD simulation. Semiconductor Science and Technology, 40(6), 1-6.

   175. Kim, M., Jang, E., Lim, J., & Shin, C. (2025). Analysis of Ring Oscillator Characteristics Induced by Line Edge Roughness Using Convolution Neural Network. IEEE Transactions on Electron Devices, 72(7), 3387-3393.

   176. Park, D., Jang, E., Choi, M., & Shin, C. (2025). Backside Contact Misalignment-Induced TDDB in BSPDN CFET. IEEE Transactions on Electron Devices, 72(9), 4648-4654.

   177. Jeong, J., Ko, K., & Shin, C., Han, J. (2025). Comprehensive Understanding of Fatigue, Breakdown, and Recovery Mechanism by Thickness Scaling in Hf0.5Zr0.5O2/Ge MF(I)S Capacitors for Low Writing Voltages. ACS Applied Electronic Materials, 7(15), 6770-6783.

   178. Lee, J., Im, S., Jeong, J., Lee, T., Park, S., & Shin, C.,  Ju, H., Kim, H. (2025). Learning hidden relationship between environment and control variables for direct control of automated greenhouse using Transformer-based model. Computers and Electronics in Agriculture, 235, 110335.

   179. Park, H., Han, C., Choi, Y., Choi, M., & Shin, C. (2025). Effect of Bottom Electrode Annealing Temperature and Atmosphere on Endurance Characteristics of Ferroelectric Hf0.5Zr0.5O2 Capacitors, IEEE Electron Device Letters, Early Access.

   180. Jeong, S., & C, Shin. (2025). Wide-Range Threshold Voltage Control of Dual-Inner-Gate Gate-All-Around Field-Effect Transistor. IEEE Transactions on Device and Materials Reliability, Early Access.

   181. Lee, C., Yoon, J., Kim, M., & C, Shin. (2025). Z-Interference Mitigation in 3-D Ferro-NAND . IEEE Transactions on Electron Devices, Early Access.