CS531: Memory Systems and Architecture
Jan - May 2024, IIT Ropar
Overview of the course
This is a specialized course on memory hierarchy design aspects of Computer Architecture.
And is open for all the students who have undertaken CS204: Computer Architecture or a similar course. The course will dive into many topics pertaining to the current state-of-the art memory design challenges related to performance, fairness, energy/power security vulnerabilities. The required basics would be revised.
This course aims to make students understand:
State of the art optimizations at Cache, Memory and Storage.
Working of non-volatile memories and their design challenges.
Working of timing-, side- and covert-channel attacks, denial-of-service attacks at memory.
Course contents*
Module 0: Introduction
Overview of the memory hierarchy in current processors
Revisiting the memory wall
Non-volatile memories
Memory based security attacks and defenses
Module 1: Cache optimizations considering Multi-core processors
Replacement policy, fairness, prefetching, etc.,
Partitioning (Static/Dynamic)
Design issues with Non-volatile memories
Module 2: Memory optimizations
Issues with DRAM
Tiered memory design
Heterogenous memory design
Row-hammer attack
Module 3: Storage architecture
Design of enterprise storage - Garbage collection, DRAM cache design, etc.,
Ransomware attack
*Few changes in the content and/or flow can be expected.
Text books:
Contents of the course will be primarily from fundamental/high-impact research papers.
Reference books:
Computer Architecture: A Quantitative Approach by David A Patterson, John L Hennessy, 5th edition.
Memory Systems: Cache, DRAM, Disk by Bruce Jacob, Spencer Ng and David Wang, 2007.
Books from Synthesis Lectures on Computer Architecture
Grading policy:
TBA
This course falls in PC-2 slot.
Class timings:
Monday, Tuesday, Wednesday: 10 to 10.50PM
Venue: CS - SH
Lectures
TBA